From models to controllers integrating graphical animation in FPGA through automatic code generation

This work aims to automatically generate process controllers' VHDL implementation code amenable to be deployed into a platform integrating graphical synoptic updating. These controllers will be implemented on FPGA based reconfigurable platforms, incorporating dedicated graphical interfaces and input/output interfaces allowing its physical connection to the process under control. The system controller behavior is modeled using IOPT Petri Nets models. A tool called Animator4FPGA was developed, which achieved this goal in cooperation with other tools developed within FORDESIGN project, namely an IOPT Petri nets graphical editor, the Animator tool, and an automatic code generation tool from Petri nets to VHDL code.