Design of synchronous circuits with multiple clocks

A theoretical framework for the analysis and synthesis of synchronous circuits with multiple periodic clocks is provided for the first time. A realization condition is derived for the implementation of an arbitrary state machine M of period p as a synchronous circuit with phased clocks. The realization condition is generally satisfied only by a multicode assignment. The set of paths of length p-1 in the state graph of M define a state machine M/sup p/ which is both equivalent to M and is p-phase realizable. A procedure is given for the merging of states of M/sup p/ to provide multicode assignments for M leading to realizations with bounded numbers of internal state variables.