Logic block and routing considerations for a new SRAM-based FPGA architecture

The XC5000 family of devices embodies the first Field Programmable Gate Array (FPGA) architecture optimized for sub-micron, three-layer-metal process technology. The architecture features a logic block structure with both coarse-grained and fine-grained elements and a rich hierarchy of routing resources. The I/O blocks are isolated from the core array to increase routability and facilitate process shrinks.