Toward the integration of incremental physical synthesis optimizations

In high-frequency microprocessor design, placement plays a significantly different role from that in large ASICs. Not only does it have to find a good global placement solution, placement needs tighter interaction with physical optimizations to improve every picosecond possible. This paper will introduce practical placement techniques that integrate buffering and gate sizing to maximize timing improvement in a standard-cell library based high-performance design flow. Combined with accurate timing models and analysis, these incremental placement techniques simultaneously consider multiple optimization options and make timing-optimal changes under the given timing model. These techniques are equipped with a “Do-no-harm” policy that makes them applicable in incremental optimization frameworks to reform critical subcircuits.