Cache-based motion estimation architecture for real-time HDTV Encoding with H.264/AVC

This paper describes an innovative, pipelined, cache-based architecture for a motion estimation coprocessor based on a predictive/recursive algorithm whose computational complexity is low and independent from the search window. The algorithm and the associated architecture yields itself very well to low-power, low-cost video capture devices with low processing capabilities, such as mobile phones, PDAs, or handhelds. The synergy between architecture and algorithmic features allows a high quality output, low memory to cache bandwidth requirements, and a search window independent implementation for H.264/AVC real time video encoding of up to high definition video (HDTV).