High-frequency systolic broadband beamforming using polyphase 3D IIR frequency-planar digital filters with interleaved A/D sampling

A massively-parallel polyphase systolic array processor is proposed for broadband beamforming using a 3D IIR space-time digital frequency-planar filter that is capable of operating at a throughput of M 2D spatial frames every clock cycle, where M is the number of (poly)phases. The method achieves an M-fold increase in throughput relative to previously known architectures, and has the potential to achieve highly-selective broadband radio-frequency (RF) digital beamforming at frame rates that are several times greater than the clock rate of the VLSI system. The practical real-time performance of the processor is demonstrated using a 3×3 section of a systolic array (that is part of a larger systolic N
1
× N
2
≈100 × 100 system), consisting of a locally-interconnected matrix of 9 identical fully-pipelined speed-optimized two phase (M=2) parallel processors on a Xilinx Sx35 FPGA device, having a corresponding measured spatial frame-rate of 100 million frames/second, when clocked at 50 MHz.