Near-linear wirelength estimation for FPGA placement

As the precise wire length for a given placement can only be known after routing, accurate and fast to compute wirelength estimates are required by FPGA placement algorithms. In this paper, we describe a new model, called star+, for estimating wire length during FPGA placement. The proposed model is continuously differentiable and can be used with both analytic and iterative improvement placement methods. Moreover, the time to calculate incremental changes in cost from moving/swapping blocks can always be computed in O(1) time. When incorporated into the well-known VPR framework, and tested using the 20 MCNC benchmarks, the results produced show that the star+ model achieves a 6-9% reduction in critical-path delay compared with HPWL, while requiring roughly the same amount of computational effort.