Tutorial: SoC Power Management Verification and Testing Issues

Power consumption has become one of the most important differentiating factors for semiconductor products. Voltage is the strongest handle for managing chip power consumption. We look in detail at some of key power management techniques such as power gating, adaptive voltage scaling and active body-bias that leverage voltage as a handle. We discuss the implications of power management architecture design, partitioning and new challenges in functional validation. The characteristics of new power states in such designs and some techniques used for their validation are examined. We also look at some design techniques to address power issues in testing. We use design examples from mobile baseband and application processor arena to explain these points.