A 7.2mW quadrature GPS receiver in 0.13µm CMOS

New design techniques are needed for ultra-low-power battery-operated CMOS transceivers with ever-shrinking minimum feature sizes and power supply voltages. A fully-integrated low-IF receiver front-end for GPS applications (Fig. 24.8.1) is presented that addresses this challenge. Integrated in 0.13µm CMOS, its key attribute is µ3X lower power than any previous design: The RF front-end, PLL, IF amplifiers and continuous-time (CT) quadrature ΔΣ ADC consume 1mW, 0.2mW, 1mW, and 5mW, respectively. The RF front-end exploits current reuse in a stacked quadrature LNA-mixer-VCO (QLMV) cell [1]. In addition, it employs double-balanced mixers and features a novel gate-modulated VCO topology for quadrature signal generation that provides low phase noise, high quadrature accuracy and low power. A second-order bandpass CT ADC achieves low power using a quadrature feedback architecture with polyphase filters, resistor DACs and continuous-time comparators.