Planar polysilicon TFT low-voltage flash memory cell with Al2O3 tunnel dielectric and (Ti,Dy) O control dielectric for three-dimensional integration

High-density nonvolatile memory applications can benefit tremendously from three-dimensional (3D) integration with low power consumption. Among several proposals, the planar polysilicon thin-film transistor (TFT) with metal nanocrystals (NCs) and high-k gate-stack is one of the promising candidates. Metal NCs were introduced to allow thin tunnel dielectric, lower the program/erase (P/E) voltage and enhance the cycle endurance. One of the key device designs is to achieve a uniform ultra-thin-body channel region without implant dopant activation, where the threshold voltage V
_th
is less affected by traps in the polysilicon grain boundaries due to the reduced volume to be depleted before inversion. Moreover, reduced surface roughness by full-wafer chemical mechanical polishing (CMP) leads to improved device characteristics and reliable process integration.