Physics-based compact model of III-V heterostructure FETs for digital logic applications

A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.