On the sub-nm EOT scaling of high-κ gate stacks

Incorporating recent data for the Si/SiO
₂
and SiO
₂
/HfO
₂
interface properties, we simulate the impact of band-gap and permittivity transitions on high-k (HK) gate-stack (GS) metal-oxide-semiconductor (MOS) devices, scaled according to the requirements for effective oxide thickness (EOT) reduction in bulk MOSFETs. Si/SiO
₂
transition effects dominate, lowering the EOT, increasing over 10 times gate leakage, and shifting over 20% of electrons from the 2-fold, to the 4-fold degenerate valley. Accounting for the interface transition effects is important for accurate HKGS device characterisation and predictive modelling.