A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

We report two DPLLs fabricated in a standard 65 nm bulk CMOS process. One PLL, targeting 1-to-2 GHz clock generation for the ASIC consumer market, is realized using a 5-stage static CMOS-ring digitally-controlled oscillator (ring-DCO). The second PLL, an exploratory design for 20-to-30 GHz applications, is realized using an LC-tank DCO. Both PLLs use the same proportional-integral (PI) loop filter, DeltaSigma modulator (DeltaSigmaM), multi-modulus feedback divider and bang-bang phase and frequency detector (BB-PFD).