Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications

The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in 10% R.O. speed improvement. When combined with high-stress contact-etch-stop-layer (CESL) scheme, a significant 27% CMOS enhancement is achieved through preferable strain superposition. Both device integrity and reliability are carefully evaluated and neither of them is adversely impacted by DTE.