Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

This paper reports a novel approach to implement low V
t
Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5Å) can lower the NiSi FUSI nFET V
t
by 300mV/500mV on HfSiON/SiON (resulting in a V
t,lin
of 0.25V/0.18V respectively), w/o compromising the T
inv
(≪1Å variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower V
t
, greatly-improved PBTI and 150x lower J
g
wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low V
t
CMOS using either dual phase (NiSi, Ni
32
Si
12
) or single phase (Ni
2
Si) FUSI gate for both n- and pFETs.