Technology Elements and Chip Design for Low Power Applications

We present transistor and technology design considerations specific to low power applications from 90nm to 45nm and beyond. We discuss static power and low standby power (LSTP) transistors, and also touch on dynamic power dissipation and low operating power (LOP) transistors. As semiconductor transistor technology is encountering several intransigent limits (voltage scaling and overdrive, and gate leakage in particular), cost-effective means of producing superior chips are enhanced by chip design techniques as much or more than by silicon technology elements