Abstract:
This paper describes the behavior of the synthesis of several adders with different structures: lineal, like ripple carry adder, tree, like carry look ahead; array, like ...Show MoreMetadata
Abstract:
This paper describes the behavior of the synthesis of several adders with different structures: lineal, like ripple carry adder, tree, like carry look ahead; array, like prefix adders; and optimized low level logic over FPGAs. The results of used resources and total delay of the resulting circuit are compared over the commercial families VIRTEX4 and STRATIX2 from Xilinx and Altera manufacturers, respectively
Published in: International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.
Date of Conference: 05-07 September 2006
Date Added to IEEE Xplore: 16 October 2006
Print ISBN:0-7803-9726-6