Contents I. INTRODUCTION
Inside the methodology of rapid prototyping in DSP, FPGAs are acquiring a very important role. So much that the devices of last generation include specific circuitry for the implementation of the DSP operations, as much the operation as the width of the used operands. Among the operations hurried by hardware, one is the sum; this one, in spite of its simplicity, is very important in DSP field, being broadly described in the bibliography [1] [2]. However these whole different structures used conventionally (Ripple Carry Adder, Carry Select Adder, Carry Look Ahead, Prefix Adders,…) to increase the yield of the sum can lose their qualities when they are mapped on a prebuilt circuit like a FPGA. The current tendency is the use of FPGAs of coarse grain, that is to say, the minimum logic blocks is able to generate very complex logic functions with multiple inputs. The main advantage consists in that decreases the number of logic blocks needed for implementing a function, that is, there are less necessary transmission lines, the true problem in a FPGA. At the same time this capacity of being able to introduce many variables in a single block can produce the lost the structure described initially in the high level stage.
