Abstract:
A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring...Show MoreMetadata
Abstract:
A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC
Date of Conference: 15-17 June 2006
Date Added to IEEE Xplore: 20 February 2007
Print ISBN:1-4244-0006-6
Contents 