Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application

Sub-1nm EOT and high electron mobility were realized at the same time with HfSi
_x
/HfO
₂
gate stacks. It was revealed that there exist two mobility degradation modes depending on the HfO
₂
thickness and the HfSi
_x
composition. One is the crystallization in the thick HfO
₂
case (Tinv > 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate (bottom-IFL) in the thin HfO
₂
case (Tinv < 1.6 nm) for the Hf-rich electrode. We have demonstrated that carefully optimizing the HfO
₂
thickness and introducing a novel "Si extrusion" process from the HfSi
_x
electrode can suppress both modes. As a result, a high electron mobility equivalent to n
⁺
poly-Si/SiO
₂
(248 cm
²
/Vs @ Eeff = 1 MV/cm) was obtained at the sub-1nm EOT region for the very first time. The successful scaling together with a well-controlled Vth roll-off led to an extremely high Ion of 1165 μA/μm (@ Ioff = 81 nA/μm) at Vdd = 1.0V for a 45nm gate nMOSFET