Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (V
_t
) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate stack stability. The new AlN cap layers provide better PFET V
_t
control than, for example, Al
₂
O
₃
layers, and can be removed from NFETs without impacting device properties. We thus have achieved sub-100 nm device V
_t
of 0.3-0.4 V with PFETs I
_on
~ 140 μA/μm at I
_off
~13 pA/μm, suitable for low-power technologies. Carrier mobilities are close to those of SiON control devices. Thus the V
_t
problem impeding the implementation of poly-Si/high-k gate stacks for low power device applications has been resolved