Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies

This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using sub-threshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5times (for bulk) and ~3.8times (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation