Energy-efficient cache architecture for multimedia applications

Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Data caches also consume a significant portion of total processor power for multimedia applications because they are data intensive. In this paper, we propose two mechanisms to reduce dynamic power consumption for both instruction and data caches. The hotspot cache adds a small cache between the CPU and L1 instruction. It identifies frequently accessed instructions dynamically and stores them in the L0 cache. The software-controlled cache architecture improves the energy efficiency of the data cache by allocating data types in an application to different cache regions. On each access, only the allocated cache regions need to be activated. We find that on the average, the hotspot cache and software-controlled cache can achieve 52% and 40% energy reduction on instruction and data caches, respectively. Both schemes incur little performance degradation.