A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage
$( V_ th)$
, and drain-induced barrier-height lowering are numerically calculated for the device with different channel length (
$L$
) and the thickness of silicon film
$( T_ si)$
. Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs,
$ T_ si$
should be simultaneously scaled down with respect to
$L$
. From a practical fabrication point-of-view, a DG MOSFET with ultrathin
$ T_ si$
will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that
$ L/ T_ si geq 1$
may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.