A semi-custom design of branch address calculator in the IBM power4 microprocessor

In this paper we present the design and implementation of the branch address calculator in the instruction fetch unit (IFU) of the IBM power4 microprocessor which operates at 1.7 GHz in a 0.18 /spl mu/m SOI technology. A semi-custom methodology combining flexible custom circuit design with automated tuning and physical design tools is shown to provide new opportunities for optimization of designs throughout the development cycle. The resulting branch calculator design supports a 3-cycle taken-branch redirect, which is key to the IFU performance in power4 microprocessor. It is shown that with careful circuit optimization, high performance can be achieved with a robust, tuned static design, thereby maintaining a power efficient design point.