A low-jitter wideband multiphase PLL in 90nm SOI CMOS technology

A multiphase PLL, implemented in 90nm SOI CMOS, covers a frequency range from 4.3 to 7.4GHz at a supply voltage of 1V. The ring oscillator-based PLL shows an in-band phase noise of up to -113dBc/Hz at 1 MHz offset and a supply noise rejection of 0.23%delay/%supply due to the rigorous application of CML-type circuit topologies combined with replica biasing.