A 22 Gbit/s PAM-4 receiver in 90 nm CMOS-SOI technology

A receiver for PAM-4 encoded data signals is presented, which was measured to receive data at 22 Gbit/s with a BER <10/sup -12/ at a maximum frequency deviation of 350 ppm and a 2/sup 7/-1 PRBS pattern. We propose a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. A CML biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. Measured current consumption is 207 mA from a 1.1 V supply, active chip area is 0.12 mm/sup 2/.