Charge trapping in aggressively scaled metal gate/high-k stacks

A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T/sub inv/, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO/sub 2/, HfO/sub 2/:N, HfSiO, HfSiON, ZrO/sub 2/, Al/sub 2/O/sub 3/); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.