A fast adaptive heuristic for FPGA placement

The time to compile current field programmable gate arrays (FPGAs) can easily take hours or even days to complete for large (8-million gate) chips, which may nullify the time-to-market advantage of FPGAs. This paper presents a novel adaptive placement heuristic that significantly reduces the amount of computation time required to achieve high-quality placements, compared with the state-of-the-art placement and routing tool, VPR. Like VPR, our algorithm is based on simulated annealing (SA). However, we include a special type of short-term memory that dramatically improves the convergence rate of the traditionally slow SA algorithm. Our experimental results show (on average) a 70% reduction in runtime while still achieving very high-quality placements.