Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]

The performance of mixed-mode ICs can be severely limited by the substrate noise that is generated by digital circuits. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate this substrate noise need to be well understood. In this paper, we show that with technology scaling substrate noise due to power-supply-line coupling becomes the dominant coupling mechanism, which is several orders of magnitude larger than the substrate noise due to the source/drain capacitive coupling and the impact ionization. Further, we show that the peak value of the power-supply-line coupling noise becomes more dependent on the switching activity ratio of the circuit rather than the Ldi/dt noise as a result of the decrease in switching time with technology scaling. These insights are believed to be very useful for the development of low-noise digital design techniques in future CMOS technologies.