A low power NORA circuit design technique based on charge recycling

In this paper we present a low power oriented design technique for NORA clocked circuits. This technique is based on a new switching scheme for charge recycling among circuit nodes. According to our approach and the corresponding simulations in a 0.18/spl mu/m CMOS technology, a maximum energy dissipation reduction of 19 % is reported while energy*delay product savings up to 14 % can be achieved.