Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

Device design of the super-halo asymmetric vertical pass transistor embedded in a cost-efficient, litho-friendly 8F/sup 2/ DRAM cell is described. This device not only retains the double-gate feature that provides twice the drive current, but also improves write-back performance critical for DRAM applications while meeting the stringent 1 fA off-current requirement. The key to achieving this degree of optimization is a super-halo angled Vt implant that produces multi-dimensionally graded well doping. The lateral grading provides small body effect and superior write-back performance that facilitates scaling with low wordline swings. The vertical grading leads to reduced short channel effect and de-coupled channel and node doping that not only reduces junction leakage but also allows aggressive scaling of the vertical device channel length.