A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices

In this paper, we present a novel low power 4 Transistor Schmitt Trigger (4T-ST) for asymmetric double gate fully depleted silicon-on-insulator (DGFDSOI) devices. The new ST is compared to conventional 6 Transistor Schmitt Trigger (6T-ST) scheme realized with symmetric (SymD) and asymmetric devices (AsymDs). Power dissipation and gate area are reduced by switching from conventional scheme to proposed scheme at iso noise-immunity (isoNT) and comparable delay.