A 3.5 ns, 1 Watt, ECL register file

A 36-b (32-b words with byte parity) by 32-word triple-ported register file designed to be used as a macrocell in an emitter-coupled-logic (ECL) reduced-instruction-set-computer (RISC) microprocessor is discussed. The goal was to produce a dense, low-power design, since the floating-point coprocessor requires two register files. The chips are fabricated using a 2- mu m, triple-implanted, three-level metal bipolar process. This process yields small, low-capacitance transistors, ideal for running at low currents. The minimum-size transistor has a collector series resistance of 1500 Omega , so transistor sizing is very important in this technology. A standard ECL inverter running at an 80- mu A tail has a nominal delay of 350 ps. The metal pitches are 4 mu m on metal 1 and metal 2 and 8 mu m on metal 3.<
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