By Topic

# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Reconfigurable Inductorless Wideband CMOS LNA for Wireless Communications

Publication Year: 2017, Page(s):675 - 685
| | PDF (2398 KB) | HTML

Future hyper-connected devices must support several communication standards, across various frequency bands, with a low-area, single-chip, radio frequency frontend. In this paper, we present a reconfigurable, inductorless, wide-band, low-noise amplifier (LNA) for multistandard applications. This LNA is based on a complementary current-reuse common source amplifier, combined with a low-current acti... View full abstract»

• ### A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Publication Year: 2017, Page(s):310 - 321
| | PDF (3650 KB) | HTML

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a ... View full abstract»

• ### A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

Publication Year: 2017, Page(s):1164 - 1172
| | PDF (2048 KB) | HTML

In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting ... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (240)  |  Patents (2)
| | PDF (1168 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Kron Reduction of Graphs With Applications to Electrical Networks

Publication Year: 2013, Page(s):150 - 163
Cited by:  Papers (98)
| | PDF (3757 KB) | HTML

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic ci... View full abstract»

• ### An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS

Publication Year: 2017, Page(s):1094 - 1105
| | PDF (3700 KB) | HTML

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DC... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (99)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (775)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### Analysis and Design of VCO-Based Phase-Domain $\Sigma \Delta$ Modulators

Publication Year: 2017, Page(s):1075 - 1084
| | PDF (1782 KB) | HTML

VCO-based phase-domain ΣΔ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional ΣΔ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of ... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (224)  |  Patents (12)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Publication Year: 2017, Page(s):869 - 878
| | PDF (3050 KB) | HTML

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at... View full abstract»

• ### A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS

Publication Year: 2017, Page(s):562 - 572
| | PDF (4522 KB) | HTML

This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by √(3/2) in theory compared with the conventional approach. By employing majority-vote comparison at the co... View full abstract»

• ### A Self-Powered and Optimal SSHI Circuit Integrated With an Active Rectifier for Piezoelectric Energy Harvesting

Publication Year: 2017, Page(s):537 - 549
| | PDF (2585 KB) | HTML

This paper presents a piezoelectric energy harvesting circuit, which integrates a Synchronized Switch Harvesting on Inductor (SSHI) circuit and an active rectifier. The major design challenge of the SSHI method is flipping the capacitor voltage at optimal times. The proposed SSHI circuit inserts an active diode on each resonant loop, which ensures flipping of the capacitor voltage at optimal times... View full abstract»

• ### A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

Publication Year: 2017, Page(s):1308 - 1317
| | PDF (3114 KB) | HTML

This paper presents a precision bandgap reference with an innovative adjusted-temperature-curvature compensation circuit that obtains a good temperature coefficient (TC) over a wide temperature range. The proposed compensation circuit for enhancing the voltage accuracy of the bandgap reference combines an addition circuit, subtraction circuit, and current mirror to achieve an adjusted piecewise li... View full abstract»

• ### A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems

Publication Year: 2017, Page(s):992 - 1002
| | PDF (3861 KB) | HTML

A self-body-biasing technique is proposed for differential-drive cross-coupled (DDCC) rectifier, with its profound application in far-field RF energy-harvesting systems. The conventional source-to-body, and the proposed technique known as Lower DC Feeding (LDCF), were fabricated in the 130-nm CMOS and compared at the operation frequency of 500 MHz, 953 MHz and 2 GHz along with a corresponding load... View full abstract»

• ### A Chopper Instrumentation Amplifier With Input Resistance Boosting by Means of Synchronous Dynamic Element Matching

Publication Year: 2017, Page(s):753 - 764
| | PDF (2758 KB) | HTML

In this work, we propose a method to increase the parasitic input resistance caused by application of chopper modulation to indirect current feedback instrumentation amplifiers. The result is obtained by applying dynamic element matching to the input and feedback ports at the same frequency as chopper modulation. The proposed approach requires effective offset ripple rejection and equalization of ... View full abstract»

• ### Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems

Publication Year: 2017, Page(s):1019 - 1030
| | PDF (4238 KB) | HTML

In this work we investigate a new background calibration technique to compensate sampling phase errors in time-interleaved analog-to-digital-converters (TI-ADCs). Timing mismatches in TI-ADC degrade significantly the performance of ultra-high-speed digital transceivers. Unlike previous proposals, the calibration technique used here optimizes a metric directly related to the performance of the comm... View full abstract»

• ### An All-Digital, Single-Bit RF Transmitter for Massive MIMO

Publication Year: 2017, Page(s):696 - 704
| | PDF (2228 KB) | HTML

This paper presents an all-digital transmitter solution particularly suited for Massive multiple-input and multiple-output (MIMO) systems for mobile communications. Massive MIMO is a key candidate to address the challenges of future mobile communication standards, especially to provide higher capacity in dense urban scenarios. While the required communication theory is elaborated to a great extend... View full abstract»

• ### A Power-Efficient Reconfigurable Output-Capacitor-Less Low-Drop-Out Regulator for Low-Power Analog Sensing Front-End

Publication Year: 2017, Page(s):1318 - 1327
| | PDF (1805 KB) | HTML

A power efficient reconfigurable output-capacitorless (OCL) low-drop-out (LDO) voltage regulator for low-power analog sensing front-end is proposed in this paper. This LDO consists of a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. The error amplifier adopts a class-AB input differential ... View full abstract»

• ### Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

Publication Year: 2010, Page(s):2353 - 2366
Cited by:  Papers (83)  |  Patents (2)
| | PDF (2929 KB) | HTML

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 an... View full abstract»

• ### A Nonlinear Switched State-Space Model for Capacitive RF DACs

Publication Year: 2017, Page(s):1342 - 1353
| | PDF (5199 KB) | HTML

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal-oxide-semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current-voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compare... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (136)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### A ± 3 ppm/°C Single-Trim Switched Capacitor Bandgap Reference for Battery Monitoring Applications

Publication Year: 2017, Page(s):777 - 786
| | PDF (3418 KB) | HTML

A precision bandgap reference has been developed in a 0.18 μm BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 o from -40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a 2nd order delta-sigma modulator ADC to digitize ... View full abstract»

• ### Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Publication Year: 2017, Page(s):1173 - 1186
| | PDF (3888 KB) | HTML

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related to the input size; 2) their performance degrades seriously when operated in near-Vt regime. Resistive Random Access Memory (RRAM) technology bri... View full abstract»

• ### A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

Publication Year: 2016, Page(s):1616 - 1627
Cited by:  Papers (1)
| | PDF (3640 KB) | HTML

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 7... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (371)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance

Publication Year: 2017, Page(s):836 - 846
| | PDF (5950 KB) | HTML

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the sa... View full abstract»

• ### A frequency compensation scheme for LDO voltage regulators

Publication Year: 2004, Page(s):1041 - 1050
Cited by:  Papers (150)  |  Patents (6)
| | PDF (576 KB) | HTML

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capa... View full abstract»

• ### A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter

Publication Year: 2017, Page(s):1106 - 1117
| | PDF (2878 KB) | HTML

A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a cou... View full abstract»

• ### Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Publication Year: 2011, Page(s):22 - 36
Cited by:  Papers (106)  |  Patents (2)
| | PDF (1569 KB) | HTML

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization iss... View full abstract»

• ### A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (33)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• ### Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation

Publication Year: 2015, Page(s):2759 - 2770
Cited by:  Papers (4)
| | PDF (2893 KB) | HTML

Recent developments in CMOS passive mixers have demonstrated a number of new and useful capabilities, including dynamic RF port impedance control and filter up-conversion, while also allowing low noise figure and high out-of-band linearity, all of which track wide-ranging LO frequencies and tunable baseband bandwidth. However, these circuits also bring a unique set of challenges and requirements. ... View full abstract»

• ### Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation

Publication Year: 2017, Page(s):1626 - 1635
| | PDF (2292 KB) | HTML

This paper presents a new transformer-feedback technique for RF and millimeter-wave (mmW) low-noise amplifiers (LNAs). The working principle of conventional LNAs using transformers is analyzed to show their underlying performance trade-off between input matching and noise figure (NF). To mitigate this issue, a new feedback technique is developed by constructing a drain-to-gate feedback path around... View full abstract»

• ### Theory and applications of incremental ΔΣ converters

Publication Year: 2004, Page(s):678 - 690
Cited by:  Papers (122)  |  Patents (9)
| | PDF (416 KB) | HTML

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (ΔΣ) structures used in telecommunication and audio applications usually ... View full abstract»

• ### A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems

Publication Year: 2017, Page(s):217 - 226
| | PDF (3502 KB) | HTML

Miniaturized thin-film thermoelectric generators (TEGs) are emerging energy harvesting sources suitable for wearable and implantable applications. However, these sources usually exhibit large internal equivalent series resistance (ESR) that leads to low energy conversion efficiency and self-startup failures at ultra-low voltages. This paper presents a highly efficient boost converter with a novel ... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (13)
| | PDF (2674 KB) | HTML

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### An Energy Autonomous 400 MHz Active Wireless SAW Temperature Sensor Powered by Vibration Energy Harvesting

Publication Year: 2015, Page(s):976 - 985
Cited by:  Papers (4)
| | PDF (2450 KB) | HTML

An energy autonomous active wireless surface acoustic wave (SAW) temperature sensor system is presented in this paper. The proposed system adopts direct temperature to frequency conversion using a lithium niobate SAW resonator for both temperature sensing and high-Q resonator core in a cross-coupled RF oscillator. This arrangement simplifies the temperature sensor readout circuit design and reduce... View full abstract»

• ### A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

Publication Year: 2017, Page(s):1673 - 1683
| | PDF (2382 KB) | HTML

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrappe... View full abstract»

• ### Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design

Publication Year: 2017, Page(s):1 - 13
| | PDF (2202 KB)

Chopping is a commonly used technique to eliminate flicker noise in amplifiers. We investigate the use of chopping in the input integrator of a continuous-time oversampling (ΔΣ) converter. Unlike an amplifier, the integrator in a continuous-time delta-sigma modulator is subject to out-of-band signals that are several orders of magnitude higher than the (desired) in-band component. Th... View full abstract»

• ### A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer

Publication Year: 2017, Page(s):1085 - 1093
| | PDF (3056 KB) | HTML

A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage sw... View full abstract»

• ### Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves

Publication Year: 2017, Page(s):86 - 99
| | PDF (2769 KB) | HTML

To the best of our knowledge, we present the first hardware implementation of isogeny-based cryptography available in the literature. Particularly, we present the first implementation of the supersingular isogeny Diffie-Hellman (SIDH) key exchange, which features quantum-resistance. We optimize this design for speed by creating a high throughput multiplier unit, taking advantage of parallelization... View full abstract»

• ### Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Publication Year: 2012, Page(s):3 - 29
Cited by:  Papers (120)
| | PDF (1561 KB) | HTML

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is acc... View full abstract»

• ### Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

Publication Year: 2017, Page(s):1637 - 1650
| | PDF (3613 KB)

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps ... View full abstract»

• ### First Principles Optimization of Opto-Electronic Communication Links

Publication Year: 2017, Page(s):1270 - 1283
| | PDF (3184 KB) | HTML

We introduce a first principles, end-to-end analysis of opto-electronic communication links which incorporates a thorough model of the receiver circuitry, in addition to the more familiar laser transmitter optimization. In particular, we optimize receiver sensitivity and power by studying their dependence on front-end design as well as follow-on digital sampler requirements. We find that the photo... View full abstract»

• ### A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing

Publication Year: 2017, Page(s):1 - 14
| | PDF (2773 KB)

This paper presents a discrete time 2-1 MASH Delta-Sigma (ΔΣ) modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers. Through the allocation of different settling times to the opamps and by adopting the multirate technique, the power of the shared opamps is utilized more e... View full abstract»

• ### High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger

Publication Year: 2017, Page(s):1003 - 1012
| | PDF (3168 KB) | HTML

In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling... View full abstract»

• ### A Study of Injection Locking in Dual-Band CMOS Frequency Dividers

Publication Year: 2017, Page(s):1225 - 1234
| | PDF (2177 KB) | HTML

We present a study of dual-band injection locking frequency dividers (ILFDs), based on a nonlinear analysis. We develop a quasi-normal model of these dividers suitable for applying the method of averaging, which allowed us to derive in a simple and expressive manner the first-approximation equations for the amplitudes and phases of the locked modes, both in transient and in steady state. The phase... View full abstract»

• ### Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Publication Year: 2017, Page(s):245 - 260
| | PDF (3029 KB) | HTML

Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multip... View full abstract»

• ### Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach

Publication Year: 2017, Page(s):347 - 359
| | PDF (2894 KB) | HTML

Passive mixers have become an essential component of SAW-less communication receivers in the last few years, this has encouraged many researchers to study their impedance characteristics. When observed from the input radio frequency (RF) port of the passive mixer, the impedance exhibits bandpass filtering characteristics centered around the frequency of the local oscillator (LO) signal. The theory... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (89)  |  Patents (6)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless te... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK