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Popular Articles (March 2015)

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  • 1. Reconfigurable Terahertz Leaky-Wave Antenna Using Graphene-Based High-Impedance Surface

    Publication Year: 2015 , Page(s): 62 - 69
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (909 KB) |  | HTML iconHTML  

    The concept of graphene-based two-dimensional leaky-wave antenna (LWA), allowing both frequency tuning and beam steering in the terahertz band, is proposed in this paper. In its design, a graphene sheet is used as a tuning part of the high-impedance surface (HIS) that acts as the ground plane of such 2-D LWA. It is shown that, by adjusting the graphene conductivity, the reflection phase of the HIS can be altered effectively, thus controlling the resonant frequency of the 2-D LWA over a broad band. In addition, a flexible adjustment of its pointing direction can be achieved over a wide range, while keeping the operating frequency fixed. Transmission-line methods are used to accurately predict the antenna reconfigurable characteristics, which are further verified by means of commercial full-wave analysis tools. View full abstract»

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  • 2. Design Guidelines for Sub-12 nm Nanowire MOSFETs

    Publication Year: 2015 , Page(s): 210 - 213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material. View full abstract»

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  • 3. 3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

    Publication Year: 2015 , Page(s): 93 - 100
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1147 KB) |  | HTML iconHTML  

    Nanoscaled Si SOI FinFETs with gate lengths of 12.8 and 10.7 nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrodinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: (100) and (110). The 10.7-nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Green's functions (NEGF) technique and the results are compared with MC simulations. The 12.8 and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33- 37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a (100) channel orientation deliver a larger drive current by about 11% more than their counterparts with a (110) channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID - VG characteristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about VG - VT = 0.3 V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities. View full abstract»

    Open Access
  • 4. A Compact Analytical Model for the Drain Current of Gate-All-Around Nanowire Tunnel FET Accurate From Sub-Threshold to ON-State

    Publication Year: 2015 , Page(s): 358 - 362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    We present a compact analytical model for the drain current of a gate-all-around nanowire tunneling field effect transistor. The model takes into account the effect of oxide thickness, body doping, drain voltage, and gate metal work function. The model uses a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against three dimensional numerical simulations calibrated using experimental results. The model predicts the drain current accurately in both the on-state (strong inversion), as well as in the sub-threshold region. View full abstract»

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  • 5. Paper-Based Lithium-Ion Batteries Using Carbon Nanotube-Coated Wood Microfibers

    Publication Year: 2013 , Page(s): 408 - 412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    Lithium-ion batteries using flexible paper-based current collectors have been developed. These current collectors were fabricated from wood microfibers that were coated with carbon nanotubes (CNT) through an electrostatic layer-by-layer nanoassembly process. The carbon nanotube mass loading of the presented (CNT-microfiber paper) current collectors is 10.1 μg/cm2. The capacities of the batteries made with the current collectors are 150 mAh/g for lithium cobalt oxide (LCO) half-cell, 158 mAh/g for lithium titanium oxide (LTO) half-cell, and 126 mAh/g for LTO/LCO full-cell. The fabrication approach of the CNT-microfiber paper current collectors, the assembly of the batteries, and the experimental results are presented and discussed. View full abstract»

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  • 6. Controlling Grain Size and Continuous Layer Growth in Two-Dimensional MoS2 Films for Nanoelectronic Device Application

    Publication Year: 2015 , Page(s): 238 - 242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    We report that control over the grain size and lateral growth of monolayer MoS2 film, yielding a uniform large-area monolayer MoS2 film, can be achieved by submitting the SiO2 surfaces of the substrates to oxygen plasma treatment and modulating substrate temperature in chemical vapor deposition (CVD) process. Scanning electron microscopy and atomic force microscopy images and Raman spectra revealed that the MoS2 lateral growth could be controlled by the surface treatment conditions and process temperatures. Moreover, the obtained monolayer MoS2 films showed excellent scalable uniformity covering a centimeter-scale SiO2 /Si substrates, which was confirmed with Raman and photoluminescence mapping studies. Transmission electron microscopy measurements revealed that the MoS2 film of the monolayer was largely single crystalline in nature. Back-gate field effect transistors based on a CVD-grown uniform monolayer MoS2 film showed a good current on/off ratio of ~106 and a field effect mobility of 7.23 cm2/V·s. Our new approach to growing MoS2 films is anticipated to advance studies of MoS2 or other transition metal dichalcogenide material growth mechanisms and to facilitate the mass production of uniform high-quality MoS2 films for the commercialization of a variety of applications. View full abstract»

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  • 7. Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications

    Publication Year: 2015 , Page(s): 275 - 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (967 KB) |  | HTML iconHTML  

    CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 1012 eV-1 · cm-2. View full abstract»

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  • 8. Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET

    Publication Year: 2014 , Page(s): 627 - 629
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1038 KB) |  | HTML iconHTML  

    This letter studies the application of tunnel FET (TFET) for ultralow power image processing through cellular neural network (CNN). Through steeper switching slope, and thereby higher gm/IDS, a TFET-based CNN synapse can deliver the same performance as MOSFET even with a lower power. A TFET-based synapse is also scalable to the ultralow power regime; hence, by comprising more cells than MOSFET at the same power, TFET can reduce the multiplexing overheads in image processing with CNN. Utilizing unique properties of TFET, we show an improved performance for low power image processing using TFET. View full abstract»

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  • 9. Synthesis, Transfer, and Devices of Single- and Few-Layer Graphene by Chemical Vapor Deposition

    Publication Year: 2009 , Page(s): 135 - 138
    Cited by:  Papers (69)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    The advance of graphene-based nanoelectronics has been hampered due to the difficulty in producing single- or few-layer graphene over large areas. We report a simple, scalable, and cost-efficient method to prepare graphene using methane-based CVD on nickel films deposited over complete Si/SiO2 wafers. By using highly diluted methane, single- and few-layer graphene were obtained, as confirmed by micro-Raman spectroscopy. In addition, a transfer technique has been applied to transfer the graphene film to target substrates via nickel etching. FETs based on the graphene films transferred to Si/SiO2 substrates revealed a weak p-type gate dependence, while transferring of the graphene films to glass substrate allowed its characterization as transparent conductive films, exhibiting transmittance of 80% in the visible wavelength range. View full abstract»

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  • 10. Annealing-Free Solution-Processed Silver Nanowire-Polymer Composite Transparent Electrodes and Flexible Device Applications

    Publication Year: 2015 , Page(s): 36 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB) |  | HTML iconHTML  

    By using ultrahigh aspect ratio (>2000:1) silver nanowires (AgNWs) and ethanol-diluted poly (3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as the overcoating layer, we achieved flexible AgNW-polymer composite transparent electrodes of high conductivity and optical transmittance using facile solution processes at room temperature without annealing. The electrodes were applied in fabricating flexible capacitive pressure sensors and organic photovoltaic (OPV) devices. The pressure sensor with the composite electrodes presents three times higher sensitivity than that using ITO electrodes. A flexible 4 × 4 sensor array was also fabricated, which well proved the capability of the electrodes for spatially electronic signal collection and transmission. The fabricated flexible OPV device has a power conversion efficiency of 1.83%, which proves the potential of the electrodes for multilayer integration in optoelectronic device applications. View full abstract»

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  • 11. Wideband Modeling of Graphene-Based Structures at Different Temperatures Using Hybrid FDTD Method

    Publication Year: 2015 , Page(s): 250 - 258
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2189 KB) |  | HTML iconHTML  

    An efficient finite-difference time-domain (FDTD) algorithm is proposed for studying frequency- and temperature-dependent characteristics of some graphene-based structures, with auxiliary differential equation-FDTD method and its conformal modification technique integrated together for handling such atomically thin and electrically dispersive periodic geometries. Numerical results are presented to show their tunable transmittances, surface plasmon polarization-mode characteristics and Fano resonances, where the effects of chemical potential of graphene, biasing electric field strength, as well as operating temperature are captured and investigated in detail. View full abstract»

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  • 12. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes

    Publication Year: 2015 , Page(s): 346 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1215 KB) |  | HTML iconHTML  

    Recent trends in emerging nonvolatile memory systems necessitate efficient read/write (R/W) schemes. Efficient solutions with zero sneak path current, nondestructive R/W operations, minimum area and low power are some of the key requirements. Toward this end, we propose a novel crossbar memory scheme using a configuration row of cells for assisting R/W operations. The proposed write scheme minimizes the overall power consumption compared to the previously proposed write schemes and reduces the state drift problem. We also propose two read schemes, namely, assisted-restoring and self-resetting read. In assisted-restoring scheme, we use the configuration cells which are used in the write scheme, whereas we implement additional circuitry for self-reset which addresses the problem of destructive read. Moreover, by formulating an analytical model of R/W operation, we compare the various schemes. The overhead for the proposed assisted-restoring write/read scheme is an extra redundant row for the given crossbar array. For a typical array size of 200 × 200 the area overhead is about 0.5%, however, there is a 4X improvement in power consumption compared to the recently proposed write schemes. Quantitative analysis of the proposed scheme is analyzed by using simulation and analytical models. View full abstract»

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  • 13. Use of Terahertz Photoconductive Sources to Characterize Tunable Graphene RF Plasmonic Antennas

    Publication Year: 2015 , Page(s): 390 - 396
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    Graphene, owing to its ability to support plasmon polariton waves in the terahertz frequency range, enables the miniaturization and electrical tunability of antennas to allow wireless communications among nanosystems. One of the main challenges in the characterization and demonstration of graphene antennas is finding suitable terahertz sources to feed the antenna. This paper characterizes the performance of a graphene RF plasmonic antenna fed with a photoconductive source. The terahertz source is modeled and, by means of a full-wave EM solver, the radiated power as well as the tunable resonant frequency of the device is estimated with respect to material, laser illumination, and antenna geometry parameters. The results show that with this setup the antenna radiates terahertz pulses with an average power up to 1 μW and shows promising electrical frequency tunability. View full abstract»

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  • 14. Electrothermal Characterization of Multilevel Cu-Graphene Heterogeneous Interconnects in the Presence of an Electrostatic Discharge (ESD)

    Publication Year: 2015 , Page(s): 205 - 209
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (725 KB) |  | HTML iconHTML  

    Temperature responses of multilevel Cu-graphene heterogeneous interconnects under the impact of an electrostatic discharge are investigated by using our self-developed time-domain finite-element method algorithm. Corresponding to the advanced CMOS processes, all parameters of such multilevel interconnects are assessed by the ITRS. It is numerically shown that when capped with 10-nm-thick multilayer graphene, the maximum temperature of the Cu-graphene interconnect could be suppressed by 45% and 30% for 13.4- and 21-nm nodes, respectively. This study could be useful for improving the reliability of interconnects in the future nanoscale integrated circuits. View full abstract»

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  • 15. Graphene Terahertz Plasmon Oscillators

    Publication Year: 2008 , Page(s): 91 - 99
    Cited by:  Papers (136)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    In this paper we propose and discuss coherent terahertz sources based on charge density wave (plasmon) amplification in two-dimensional graphene. The coupling of the plasmons to interband electron-hole transitions in population inverted graphene layers can lead to plasmon amplification through stimulated emission. Plasmon gain values in graphene can be very large due to the small group velocity of the plasmons and the strong confinement of the plasmon field in the vicinity of the graphene layer. We present a transmission line model for plasmon propagation in graphene that includes plasmon dissipation and plasmon interband gain due to stimulated emission. Using this model, we discuss design for terahertz plasmon oscillators and derive the threshold condition for oscillation taking into account internal losses and also losses due to external coupling. The threshold condition is shown to depend on the ratio of the external impedance and the characteristic impedance of the plasmon transmission line. The large gain values available at terahertz frequencies in graphene can lead to integrated oscillators that have dimensions in the 1-10 mum range. View full abstract»

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  • 16. Compensated Readout for High-Density MOS-Gated Memristor Crossbar Array

    Publication Year: 2015 , Page(s): 3 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array. View full abstract»

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  • 17. Two Memristor SPICE Models and Their Applications in Microwave Devices

    Publication Year: 2014 , Page(s): 607 - 616
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1085 KB) |  | HTML iconHTML  

    This paper presents two simple SPICE circuit models of the memristor using two different kinds of integrators. These models expand and simplify the previous methods of solving the memristor's modeling equations presented by Hewlett-Packard Lab. The behaviors of the two memristor models are investigated when they are excited by a sinusoidal voltage source. Both models satisfy the general features of memristive systems such as having a zero-crossing property in the form of an i-v Lissajous figure. In order to explore the unique characteristics and applications of the memristor in microwave devices, first we incorporate the memristor in a microstrip transmission line as a load. We do the analysis using a finite-difference time-domain simulator integrated with a nonlinear SPICE circuit solver. Furthermore, we design a reconfigurable microstrip bandpass filter based on a memristor-loaded resonator, and utilize a memristor as a carrier-wave modulator connecting the microstrip patch antenna to the ground. View full abstract»

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  • 18. Design of a Beam Reconfigurable THz Antenna With Graphene-Based Switchable High-Impedance Surface

    Publication Year: 2012 , Page(s): 836 - 842
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (889 KB) |  | HTML iconHTML  

    In this paper, a new beam reconfigurable antenna is proposed for THz application, which is based on a switchable high-impedance surface (HIS) using a single-layer graphene. The effects of impurity density and gate voltage on the conductivity of graphene are utilized, and the switchable reflection characteristic of the graphene-based HIS is observed. Then the THz antenna is designed over this switchable HIS. By applying different voltages for different rows of HIS units, the antenna beam can be reconfigurable. The performance of the antenna is analyzed with its reflection coefficient, radiation pattern, and input impedance. The radiation beam of the antenna can vary in a range of ±30° as demonstrated by the simulated results. View full abstract»

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  • 19. Effect of Line Defects on the Electrical Transport Properties of Monolayer MoS _{\bf 2} Sheet

    Publication Year: 2015 , Page(s): 51 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB) |  | HTML iconHTML  

    We present a computational study on the impact of line defects on the electronic properties of monolayer MoS2. Four different kinds of line defects with Mo and S as the bridging atoms, consistent with recent theoretical and experimental observations, are considered herein. We employ the density functional tightbinding (DFTB) method with a Slater-Koster-type DFTB-CP2K basis set for evaluating the material properties of perfect and the various defective MoS2 sheets. The transmission spectra are computed with a DFTB-non-equilibrium Green's function formalism. We also perform a detailed analysis of the carrier transmission pathways under a small bias and investigate the phase of the transmission eigenstates of the defective MoS2 sheets. Our simulations show a two to four fold decrease in carrier conductance of MoS2 sheets in the presence of line defects as compared to that for the perfect sheet. View full abstract»

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  • 20. Graphene-Based Plasmonic Tunable Low-Pass Filters in the Terahertz Band

    Publication Year: 2014 , Page(s): 1145 - 1153
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (754 KB) |  | HTML iconHTML  

    We propose the concept, synthesis, analysis, and design of graphene-based plasmonic tunable low-pass filters operating in the terahertz band. The proposed structure is composed of a graphene strip transferred onto a dielectric and a set of polysilicon dc gating pads located beneath it. This structure implements a stepped impedance low-pass filter for the propagating surface plasmons by adequately controlling the guiding properties of each strip section through graphene's field effect. A synthesis procedure is presented to design filters with desired specifications in terms of cutoff frequency, in-band performance, and rejection characteristics. The electromagnetic modeling of the structure is efficiently performed by combining an electrostatic scaling law to compute the guiding features of each strip section with a transmission line and transfer-matrix framework, approach further validated via full-wave simulations. The performance of the proposed filters is evaluated in practical scenarios, taking into account the presence of the gating bias and the influence of graphene's losses. These results, together with the high miniaturization associated with plasmonic propagation, are very promising for the future use and integration of the proposed filters with other graphene and silicon-based elements in innovative terahertz communication systems. View full abstract»

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  • 21. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

    Publication Year: 2011 , Page(s): 217 - 225
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (773 KB) |  | HTML iconHTML  

    This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product. View full abstract»

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  • 22. Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

    Publication Year: 2006 , Page(s): 723 - 730
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1849 KB) |  | HTML iconHTML  

    The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phiTiN) slightly decreases with increasing nitrogen (N2) gas flow ratio, RN=N2/(Ar+N2) in the sputtering, from 17% to 100%. The experimental threshold voltage (Vth) dependence on the RN shows that the more RN offers the lower Vth for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different RN showed that the more amount of nitrogen is introduced into the TiN films with increasing RN, which suggests that the lowering of phi TiN with increasing RN should be related to the increase in nitrogen concentration in the TiN film. The desirable Vth shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n+ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication View full abstract»

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  • 23. Building Memristor Applications: From Device Model to Circuit Design

    Publication Year: 2014 , Page(s): 1154 - 1162
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (627 KB) |  | HTML iconHTML  

    Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices. View full abstract»

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  • 24. Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects: An ABCD Parameter-Based Approach

    Publication Year: 2015 , Page(s): 259 - 274
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1244 KB) |  | HTML iconHTML  

    In this paper, the crosstalk effects in both small and large diameter multiwalled carbon nanotube bundle interconnects (MWCNTs) for the future nanoscale integrated circuits are studied with the help of ABCD parameter matrix approach for global levels of interconnects at 22- and 14-nm technology nodes. Here, isolated MWCNTs are modeled using an equivalent single conductor transmission line. The simulation results show that the results are at par with the result of SPICE model. It is observed that performance wise, the large diameter MWCNT bundles are better than both small diameter MWCNT bundles and copper wire for both repeated and unrepeated interconnects. The same trend is observed with the number of inserted repeaters. For repeated wires, the optimized placement of repeaters offsets the delay advantage numbers of MWCNT bundles over copper wire. Technology scaling adversely impacts the delay advantage numbers of small diameter MWCNT bundles. As far as the worst-case crosstalk noise peak voltage is concerned, the large diameter MWCNT bundles also outperform both small diameter MWCNT bundles and copper wire for longer interconnects. However, for shorter interconnects, copper wire and small diameter bundles outclass the large diameter bundles due to their relatively larger time constant. We have compared our crosstalk analysis results with the earlier work to justify the validity of our proposed model and observed that the results with our model are in well conformity with the existing work. It is seen that even the tall Cu vias are not going to significantly affect the performance of MWCNT bundle interconnects. Twice the minimum width global level interconnects are the optimal choice to achieve the maximum delay advantage using MWCNT bundle interconnects in comparison with Cu-based interconnects. Finally, our analysis shows that from the performance and signal integrity perspective, the large diameter MWCNT bundles are a suitable alternative to both small diameter - WCNT bundles and copper interconnects for future integrated circuit technology generations. View full abstract»

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  • 25. Functional-Graded Index Metasurfaces for Infrared Radiation and Guiding

    Publication Year: 2015 , Page(s): 75 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    We present the fundamental principle of plasmonic-graded-index materials for radiating and guiding at infrared range. The method to derive effective refractive index is presented and effective refractive index engineering is comprehensively investigated by obtaining complex dispersion diagrams. As an illustrative example for radiating structure, a graded index metasurface is designed for collimating the power emanating from an aperture to a steered narrow beam. The center frequency of operation is 57.5 THz. The half power beam widths of the beam radiated from a 15λ × 15λ metasurface to θ = 30° direction are 6° and 16° in elevation and azimuth planes, respectively. Radiation efficiency is calculated to be 86%. To demonstrate the guiding application, a flat step index waveguide is designed. The surface wave guiding is characterized by obtaining complex dispersion diagram and mode profiles. The applications of such waveguides in feeding antennas and routing surface waves are demonstrated with some unique designs. View full abstract»

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  • 26. Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency

    Publication Year: 2015 , Page(s): 140 - 151
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1982 KB) |  | HTML iconHTML  

    In CMOS switches, the input signal modulates the on-channel resistance for a constant gate voltage. This necessitates over design of CMOS switches. Also, further CMOS scaling in the nanometer regime has failed to improve energy efficiency due to increasing leakage energy. Looking beyond CMOS, nanoelectromechanical (NEM) relays are a promising class of emerging devices that exhibit energy-efficient switching and zero leakage operation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Numerous end applications of NEM relay logic circuits have been proposed recently, including digital logic and memory. NEMS-based miniature switches form an interesting alternative in power management integrated circuits, the area of which is primarily dominated by CMOS power transistors. This study explores discontinuous-conduction mode buck regulator with specifications suitable for portable applications using a NEMS-CMOS hybrid design, and the results are compared against a standard commercial 0.35-μm CMOS implementation. The electromechanical model has been developed for a suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm published in the literature. The model accounts for the mechanical, electrical, and dispersion effects in the relay. This study shows that NEMS-CMOS hybrid dc-dc converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100 mA. View full abstract»

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  • 27. Effect of Annealing in Ar/H2 Environment on Chemical Vapor Deposition-Grown Graphene Transferred With Poly (Methyl Methacrylate)

    Publication Year: 2015 , Page(s): 70 - 74
    Multimedia
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    Poly(methyl methacrylate) (PMMA) is widely used for transferring chemical vapor deposition grown graphene. The residue of PMMA after the transfer degrades the electronic properties of the graphene, and the complete removal of PMMA has been a challenging issue. Annealing in Ar/H2 gas flow has been commonly adopted to remove the PMMA residue. We studied the effect of annealing on graphene in the wide temperature range of 350-800 °C using Ar/H2 forming gas, systematically. The conductivity was increased at moderate temperatures, but decreased at excessive temperatures higher than 650 °C. On the other hand, the PMMA residue was not removed effectively in all temperature ranges, judging from Raman spectroscopy and atomic force microscopy. By analyzing Raman spectroscopic data, chemisorption of PMMA residue on graphene was confirmed. View full abstract»

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  • 28. Time and Frequency Domain Analysis of MLGNR Interconnects

    Publication Year: 2015 , Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (718 KB)  

    Multilayer graphene nanoribbons (MLGNRs) have potentially provided attractive solutions in an intensely growing researched area of interconnects. However, for MLGNR interconnects, the doping is inevitable since the conductivity of neutral MLGNR is much lower than even Cu. Therefore, a doped MLGNR can potentially exhibit smaller resistance in comparison to Cu wires. This paper analyzes and compares the power, delay and bandwidth performance of Cu and doped MLGNR using an equivalent single conductor (ESC) model. For similar dimensions, the overall delay and power dissipation of doped MLGNR is substantially smaller by 86.13% and 43.72%, respectively, in comparison to the Cu interconnects. Moreover, MLGNR demonstrates prominently improved bandwidth and relative stability at global interconnect dimensions. However, a narrow width MLGNR in a realistic scenario exhibits rough edges that significantly reduces the mean free path and thereby raises its resistance. Considering these facts, this paper for the first time analyzes and compares the performance of Cu and MLGNR interconnects with different edge roughness conditions. View full abstract»

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  • 29. Forming Freeform Source Shapes by Utilizing Particle Swarm Optimization to Enhance Resolution in Extreme UV Nanolithography

    Publication Year: 2015 , Page(s): 322 - 329
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    This paper investigated pixel-based source shape optimization to enhance the resolution in a projection extreme UV (EUV) lithography system. The particle swarm optimization method was proposed to optimize the source shapes. The layout patterns of the masks were corrected using model-based optical proximity correction. The optimal source shape in an EUV lithography system was verified using numerical calculations, through which the aerial image of two types of mask pattern exposure was determined. The two types of mask patterns were a logic line/space (L/S) pattern with a critical dimension (CD) of 16 nm and a SRAM contact hole (CH) pattern with a CD of 45 nm. Two significant metrics were used to evaluate the modified source performance: the latent image intensity and process window. Results from the numerical calculations showed that for L/S target patterns, using the optimal source produced a latent image error of 13.02% after exposure that was superior to that of traditional off-axis source exposure. The latent image intensity of the mask between the lines and the gaps differed substantially, corner rounding situations had effectively improved, and no bridges were observed. Concerning CH target patterns, using the optimal source produced a latent image error of 0.04% after exposure that was also superior to that of traditional sources. The latent image intensity between the holes and the gaps also differed significantly, and the latent image intensity distribution at the four corners of the CH had straight angles. Because the source shapes calculated in this study comprised pixel-based sources, the controllable microelectromechanical system mirror array chip was used to match each mirror to each pixel source, and the calculated source shapes were successfully projected. View full abstract»

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  • 30. Quantum-Dot-Based Light-Emitting Diodes With Improved Brightness and Stability by Using Sulfuric Acid-Treated PEDOT:PSS as Efficient Hole Injection Layer

    Publication Year: 2015 , Page(s): 57 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    Spin-coated poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) thin film was treated with H2SO4 and used as hole injection layer in quantum-dot-based lightemitting diodes (QD-LEDs). Such QD-LEDs with a H2SO4-treated PEDOT:PSS layer demonstrate improved carrier injection efficiency and luminance. Especially, the electroluminescence stability was greatly improved as well. Nearly 72% of peak luminance of QD-LEDs was preserved even after 24 h exposure in air for devices using H2SO4-treated PEDOT:PSS film, while a rapid loss of 98% of peak luminance within a day for untreated devices was recorded. The improved performance for QD-LEDs with H2SO4-treated PEDOT:PSS film probably originated from the conformational change of the polymer chains and the removing of the insulating and hydrophilic PSSbases from PEDOT:PSS layer. Such a simple but effective process may provide beneficial references for the development of high performance and long stability thin-film LEDs. View full abstract»

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  • 31. Impact of Receiver Reaction Mechanisms on the Performance of Molecular Communication Networks

    Publication Year: 2015 , Page(s): 304 - 317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1485 KB) |  | HTML iconHTML  

    Molecular communication networks can be used to realise communication between nanoscale devices. In a molecular communication network, transmitters and receivers communicate by using signalling molecules. At the receivers, the signalling molecules react, via a chain of chemical reactions, to produce output molecules. The counts of output molecules over time is the output signal of the receiver. The output signal is noisy due to the stochastic nature of diffusion and chemical reactions. This paper aims to characterise the properties of the output signal. We do this by modelling the transmission medium, transmitter and receiver. In order to simplify the analysis, we model the transmitter as a sequence which specifies the number of molecules emitted by the transmitter over time. This paper considers two receiver reaction mechanisms, reversible conversion and linear catalytic, which can be used to approximate, respectively, ligand-receptor binding and enzymatic reactions. These two mechanisms are chosen because, if we consider them on their own (i.e. without the transmitter and diffusion), the ordinary differential equations describing the mean behaviour of these two reaction mechanisms have the same form; however, if we consider the end-to-end behaviour from the transmitter signal to the mean/variance of the number of output molecules, then these two receiver reaction mechanisms have very different behaviours. We show this by deriving analytical expressions for the mean, variance and frequency properties of the number of output molecules of these two receiver reaction mechanisms. In addition, for reversible conversion, we are able to derive the exact probability distribution of the number of output molecules. Our model allows us to study the impact of design parameters on the communication performance. For example, we assume that our receiver is enclosed by a membrane and we study the impact of the diffusibility of molecules across this membrane on the communication p- rformance. View full abstract»

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  • 32. A Circuit Synthesis Flow for Controllable-Polarity Transistors

    Publication Year: 2014 , Page(s): 1074 - 1083
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    Double-gate (DG) controllable-polarity field-effect transistors (FETs) are devices whose n- or p- polarity is online configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotubes, and graphene technologies. Thanks to their enhanced functionality, DG controllable-polarity FETs implement arithmetic functions, such as XOR and MAJ, with limited physical resources enabling compact and high-performance datapaths. In order to design digital circuits with this technology, automated design techniques are of paramount importance. In this paper, we describe a design automation framework for DG controllable-polarity transistors. First, we present a novel dedicated logic representation form capable to exploit the polarity control during logic synthesis. Then, we tackle challenges at the physical level, presenting a regular layout technique that alleviates the interconnection issue deriving from the second gate routing. We use logic and physical synthesis tools to form a complete design automation flow. Experimental results show that the proposed flow is able to reduce the area and delay of digital circuits, based on 22-nm DG controllable-polarity Silicon nanowire (SiNW) FETs, by 22% and 42%, respectively, as compared to a commercial synthesis tool. With respect to a 22-nm FinFET technology, the proposed flow produces circuits, based on 22-nm DG controllable-polarity SiNWFETs, with 2.9 × smaller area-delay product. View full abstract»

    Open Access
  • 33. Domain Wall Memory-Layout, Circuit and Synergistic Systems

    Publication Year: 2015 , Page(s): 282 - 291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2121 KB) |  | HTML iconHTML  

    Domain wall memory (DWM) is gaining significant attention for embedded cache application due to low standby power, excellent retention, and ability to store multiple bits per cell. Additionally, it provides fast access time, good endurance, and good retention. However, it suffers from poor write latency, shift latency, shift power, and write power. DWM is sequential in nature and latency of read/write operations depends on the offset of the bit from the read/write head. This paper investigates the circuit design challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency, and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques such as merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline strapping (for access latency), shift circuit design with two micro-architectural techniques: 1) segmented cache and 2) workload-aware dynamic shift and write current boosting to realize energy-efficient and robust DWM cache. Simulations show 3-33% performance and 1.2-14.4X power consumption improvement for cache segregation and 2.5-31% performance and 1.3-14.9X power enhancement for dynamic current boosting over a wide range of PARSEC benchmarks. View full abstract»

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  • 34. The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator With Thin Box Layer MOSFETs

    Publication Year: 2015 , Page(s): 330 - 337
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability. View full abstract»

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  • 35. Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs

    Publication Year: 2014 , Page(s): 695 - 708
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3396 KB) |  | HTML iconHTML  

    Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family. View full abstract»

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  • 36. Investigation of Physically Unclonable Functions Using Flash Memory for Integrated Circuit Authentication

    Publication Year: 2015 , Page(s): 384 - 389
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    Flash memory devices are investigated to confirm their application as physically unclonable functions (PUFs). Inherent fluctuations in the characteristics of flash memory devices, even with identical fabrication processes, produce different outputs, which are useful for device fingerprints. A difference in programming/erasing efficiency arises from a widely distributed threshold voltage. However, statistical fluctuations in the threshold voltage represent an advantage for PUF applications. The characteristics of PUFs, such as their unclonability, uncontrollability, unpredictability, and robustness, are investigated using fabricated flash memory devices. A simulation study is performed to support the experimental results and to show that the unpredictability is induced by variations in the gate dielectric thickness. View full abstract»

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  • 37. Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits

    Publication Year: 2015 , Page(s): 169 - 177
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (878 KB) |  | HTML iconHTML  

    High power issues have become the main drawbacks of CMOS logic circuits as technology node shrinks below 45 nm. Emerging spintronics nanodevices-based hybrid logic-in-memory architecture has recently been investigated to overcome these issues. Among them, spin-transfer-torque-based magnetic tunnel junction (STT-MTJ) nanopillar is one of the most promising spintronics nanodevices thanks to its nonvolatility, fast access speed, and 3-D integration with CMOS technology. However, hybrid STTMTJ/CMOS logic faces severe reliability issues in ultradeep submicron technology nodes (e.g., 28 nm) due to the increasing process variations and reduced supply voltage. This paper presents architecture designs and comparative study of multicontext hybrid STT-MTJ/CMOS logic structures with a particular focus on reliability investigation. Their merits and shortcomings are demonstrated depending on the addressed applications. Finally, some design considerations and strategies are also presented to further optimize their reliability performance. Transient and Monte Carlo statistical analyses are performed by using an industrial CMOS 28-nm design kit and a physics-based STT-MTJ nanopillar compact model to exhibit their functionalities and effectiveness. View full abstract»

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  • 38. Effect of Sputtering Parameters on the Morphology of TiO2 Nanotubes Synthesized From Thin Ti Film on Si Substrate

    Publication Year: 2015 , Page(s): 18 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB) |  | HTML iconHTML  

    In this paper, we present the analysis of the properties of direct current (dc) magnetron sputtered Ti thin film that affect the morphology of TiO2 nanotubes synthesized by electrochemical anodization. Si wafer with thermally grown silicon dioxide was used as the substrate for deposition of Ti films. By varying the properties of the sputtered film, morphology of the anodized film can be varied from tubular to nanoporous TiO2. Three sputtering parameters that affect the properties of the film were studied, which include sputtering power, process gas (argon) pressure, and substrate temperature. Anodization of these films was carried out at 30 V (dc) using an ethylene glycol-based electrolyte. We show that the properties of thin film such as grain size and residual stress (bi-axial) do not affect the morphology of the anodized film and density alone influences the morphology of the anodized film. Most of the applications demonstrated by TiO2 nanotubes require annealing at high temperatures (350-800 °C) for calcination. Low residual stress in the thin film is required to prevent delaminating of the nanotubes from the substrate when exposed to high temperatures. We demonstrate that by varying the sputtering parameters, Ti films with low stress can be deposited which is required to have stable TiO2 nanotubes or nanoporous structure, based on the requirement of the application. View full abstract»

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  • 39. Robust Serial Nano-Communication with QCA

    Publication Year: 2015 , Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6898 KB)  

    We present a serial communication system implemented as quantum-dot cellular automata (QCA). QCA is a promising alternative to the current CMOS technology. It can be implemented at the nanoscale, reaching ultra-low power consumption and high clock rate. Communication systems are important in current computer systems and it is expected to be even more important in near future. Although QCA has been widely studied in the development of logic circuits, there are few studies applying this promising technology to the design of communication systems. In a bottom-up approach, we describe the Parallel-to-Serial and Serial-to-Parallel converters, which are essential to the serial communication. We also propose and present components for robust communication, such as QCA circuits for Hamming code and Parity Checker. We demonstrate the functionality, test and validate the proposed architectures using QCADesigner simulator. Due to the importance of communication systems, this study is central in consolidating QCA as a possible CMOS substitute. View full abstract»

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  • 40. Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

    Publication Year: 2012 , Page(s): 105 - 119
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2395 KB) |  | HTML iconHTML  

    The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented. View full abstract»

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  • 41. Electrostatic Doping—Controlling the Properties of Carbon-Based FETs With Gates

    Publication Year: 2014 , Page(s): 1044 - 1052
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2333 KB) |  | HTML iconHTML  

    Experimental and simulation studies on electrostatic or gate-controlled doping in carbon-based field-effect transistors are presented. As will be discussed below, the low density of states (DOS) in carbon-based materials is detrimental to the functionality of novel device concepts such as band-to-band tunnel FETs. On the other hand, the low DOS enables an excellent gate control of the conduction/valence bands. Creating appropriate doping profiles with additional gates in the source and drain regions avoids the most severe issues related to conventional doping such as the tradeoff between screening and low Fermi energy in tunnel FETs or the deactivation of dopants in nanoscale transistors. At the same time, gate-controlled doping also allows studying the electronic transport properties in carbon-based FETs such as the coupling of nanotubes and graphene to a metallic contact electrode, for instance. Furthermore, we show experimentally that with triple-gate structures TFETs with an n-i-p doping profile can be realized with electrostatic doping based on graphene nanoribbons. View full abstract»

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  • 42. Benchmarking nanotechnology for high-performance and low-power logic transistor applications

    Publication Year: 2005 , Page(s): 153 - 158
    Cited by:  Papers (232)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length Lg; 2) energy-delay product versus Lg; 3) subthreshold slope versus Lg; and 4) CV/I versus on-to-off-state current ratio ION/IOFF. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications. View full abstract»

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  • 43. Joint Energy Harvesting and Communication Analysis for Perpetual Wireless Nanosensor Networks in the Terahertz Band

    Publication Year: 2012 , Page(s): 570 - 580
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (710 KB) |  | HTML iconHTML  

    Wireless nanosensor networks (WNSNs) consist of nanosized communicating devices, which can detect and measure new types of events at the nanoscale. WNSNs are the enabling technology for unique applications such as intrabody drug delivery systems or surveillance networks for chemical attack prevention. One of the major bottlenecks in WNSNs is posed by the very limited energy that can be stored in a nanosensor mote in contrast to the energy that is required by the device to communicate. Recently, novel energy harvesting mechanisms have been proposed to replenish the energy stored in nanodevices. With these mechanisms, WNSNs can overcome their energy bottleneck and even have infinite lifetime (perpetual WNSNs), provided that the energy harvesting and consumption processes are jointly designed. In this paper, an energy model for self-powered nanosensor motes is developed, which successfully captures the correlation between the energy harvesting and the energy consumption processes. The energy harvesting process is realized by means of a piezoelectric nanogenerator, for which a new circuital model is developed that can accurately reproduce existing experimental data. The energy consumption process is due to the communication among nanosensor motes in the terahertz band (0.1-10 THz). The proposed energy model captures the dynamic network behavior by means of a probabilistic analysis of the total network traffic and the multiuser interference. A mathematical framework is developed to obtain the probability distribution of the nanosensor mote energy and to investigate the end-to-end successful packet delivery probability, the end-to-end packet delay, and the achievable throughput of WNSNs. Nanosensor motes have not been built yet and, thus, the development of an analytical energy model is a fundamental step toward the design of WNSNs architectures and protocols. View full abstract»

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  • 44. Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

    Publication Year: 2014 , Page(s): 574 - 583
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1399 KB) |  | HTML iconHTML  

    A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold. We propose spin-memristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner. Field-programmable SMTL gate arrays can operate at a small terminal voltage of ~50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks. We evaluate the performance of SMTL using threshold logic synthesis. Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array. View full abstract»

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  • 45. Comparative Analysis of Dielectric Modulated FET and TFET based Biosensor

    Publication Year: 2015 , Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1244 KB)  

    An extensive study is presented to describe the impact of partial hybridization on the device electrostatics and On current of a Silicon Dielectric Modulated Tunnel Field Effect Transistor (DM-TFET). To gain insight into the various design considerations and factors influencing the sensitivity, both process related issue such as cavity length variation and real time issues related to biomolecules behavior such as partial hybridization (PH), charge, and position of receptors/target molecules have been investigated through extensive numerical simulations. The results indicate that TFET based sensor does not suffer from scaling issues and thus can help in miniaturization without compromising the sensitivity, unlike a nanogap embedded DM-FET. View full abstract»

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  • 46. Absorption of Urea Into Zeolite Layer Integrated With Microelectronic Circuits

    Publication Year: 2015 , Page(s): 214 - 217
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB) |  | HTML iconHTML  

    A simple and efficient technique allows the direct application of a mixture of zeolite 3A and castor oil onto surfaces, at low temperatures. This same technique can also be used to fabricate iono-electronic devices on silicon wafers for biomedical purposes. In this paper, we investigate the use of a mixture of zeolite together with different vegetable oils aimed at obtaining thinner, more uniform, repeatable layers at even lower temperatures, which are capable of entrapping biological substances, specifically urea molecules. By choosing the proper mixture, the curing temperature can be optimized to make the process compatible with integrated circuit technology. A cold O2 -plasma treatment was used during experimentation to activate the zeolite thin layer on silicon, by removing the residual organic species. The absorption of urea molecules and its interaction with the zeolite framework was investigated through Fourier transform infrared spectroscopy. View full abstract»

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  • 47. The Role of Geometry Parameters and Fin Aspect Ratio of sub-20nm SOI-FinFET: An Analysis towards Analog and RF Circuit Design

    Publication Year: 2015 , Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3503 KB)  

    Now a days FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This work studies the impact of HFin and WFin variations on various performance matrices including static as well dynamic figures of merit (FOMs). With the help of Aspect Ratio (WFin/HFin). The device is branched into three parts i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the DC as well as AC figures of merit (FOMs). The static or low frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF=gm/ID), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this report can be of great help to device engineers in designing 3-D devices as per their requirement View full abstract»

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  • 48. An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

    Publication Year: 2014 , Page(s): 895 - 904
    Multimedia
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1193 KB) |  | HTML iconHTML  

    The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes. View full abstract»

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  • 49. Nanoscale memory elements based on solid-state electrolytes

    Publication Year: 2005 , Page(s): 331 - 338
    Cited by:  Papers (173)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB) |  | HTML iconHTML  

    We report on the fabrication and characterization of nanoscale memory elements based on solid electrolytes. When combined with silver, chalcogenide glasses such as Se-rich Ge-Se are good solid electrolytes, exhibiting high Ag ion mobility and availability. By placing an anode that has oxidizable Ag and an inert cathode (e.g., Ni) in contact with a thin layer of such a material, a device is formed that has an intrinsically high resistance, but which can be switched to a low-resistance state at small voltage via reduction of the silver ions. An opposite bias will return the device to a high-resistance state, and this reversible switching effect is the basis of programmable metallization cell technology. In this paper, electron beam lithography was used to make sub-100-nm openings in polymethylmethacrylate layers used as the dielectric between the device electrodes. The solid electrolyte film was formed in these via-holes so that their small diameter defined the active switching area between the electrodes. The Ag-Ge-Se electrolyte was created by the photodiffusion, with or without thermal assistance, of an Ag layer into the Ge-Se base glass. Combined thermal and photodiffusion leads to a nanophase separated material with a dispersed Ag ion-rich material with an average crystallite size of 7.5 nm in a glassy insulating Ge-rich continuous phase. The nanoscale devices write at an applied bias as low as 0.2 V, erase by -0.5 V, and fall from over 107 Ω to a low-resistance state (e.g., 104 Ω for a 10-μA programming current) in less than 100 ns. Cycling appears excellent with projected endurance well beyond 1011 cycles. View full abstract»

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  • 50. Synthesis of Atomically Thin {\bf MoS}_{\bf 2} Triangles and Hexagrams and Their Electrical Transport Properties

    Publication Year: 2014 , Page(s): 749 - 754
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    Atomically thin molybdenum disulfide (MoS2) triangles and hexagrams were prepared by a two-step growth ambient pressure chemical vapor deposition (APCVD) process. Molybdenum Trioxide (MoO3) nanobelts, a few microns in length and width, were prepared using a hydrothermal technique and utilized as the starting material. High temperature treatment of the MoO3 nanobelts followed by a rigorous sulfurization via APCVD processing provided different morphologies of MoS2 monolayers and bilayer (BL) sheets. Triangle and hexagram morphologies were characterized using Raman spectroscopy, photoluminescence (PL) measurements, scanning electron microscopy and atomic force microscopy (AFM). The regrowth step in the CVD process was proven to be ideal in enlarging the grain size. PL and Raman spectroscopy and AFM results confirmed the presence of monolayer and BL regions in the regrowth growth process. Triangle and hexagram domains are observed to be cooperatively nucleating and coalescing together to form large-area layers. Furthermore, the electrical transport properties of the synthesized MoS2 layers were studied. Electron mobility based on back gated field effect transistors was measured to be approximately 0.02 cm2/V. S. View full abstract»

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The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.

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Fabrizio Lombardi
Dept. of ECE
Northeastern Univ.