# IEEE Transactions on Device and Materials Reliability

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• ### Reliability of GaN High-Electron-Mobility Transistors: State of the Art and Perspectives

Publication Year: 2008, Page(s):332 - 343
Cited by:  Papers (313)
| |PDF (1301 KB) | HTML

Failure modes and mechanisms of AlGaN/GaN high-electron-mobility transistors are reviewed. Data from three de-accelerated tests are presented, which demonstrate a close correlation between failure modes and bias point. Maximum degradation was found in "semi-on" conditions, close to the maximum of hot-electron generation which was detected with the aid of electroluminescence (EL) measurements. This... View full abstract»

• ### Failure and Reliability Analysis of a SiC Power Module Based on Stress Comparison to a Si Device

Publication Year: 2017, Page(s):727 - 737
| |PDF (2838 KB) | HTML

The superior electro-thermal properties of silicon carbide (SiC) power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chip... View full abstract»

• ### Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

Publication Year: 2017, Page(s):213 - 220
Cited by:  Papers (2)
| |PDF (1293 KB) | HTML

Very large-scale integrated circuit design, based on today's CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leaka... View full abstract»

• ### Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

Publication Year: 2008, Page(s):501 - 508
Cited by:  Papers (20)  |  Patents (7)
| |PDF (381 KB) | HTML

Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling ... View full abstract»

Publication Year: 2005, Page(s):305 - 316
Cited by:  Papers (595)  |  Patents (6)
| |PDF (392 KB) | HTML

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creatin... View full abstract»

• ### On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

Publication Year: 2014, Page(s):536 - 544
Cited by:  Papers (6)
| |PDF (1607 KB) | HTML

CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices ac... View full abstract»

• ### Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Publication Year: 2004, Page(s):99 - 109
Cited by:  Papers (134)  |  Patents (7)
| |PDF (456 KB) | HTML

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specifi... View full abstract»

• ### Analysis of Reduction in Lag Phenomena and Current Collapse in Field-Plate AlGaN/GaN HEMTs with High Acceptor Density in a Buffer Layer

Publication Year: 2017, Page(s): 1
| |PDF (771 KB)

We make a two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs with a semi-insulating buffer layer, where only a deep acceptor above the midgap is considered. The deep-acceptor density is varied between 10¹⁷ cm¯³ and 8x10¹⁷ cm¯³. It is studied how the deep-acceptor density and the field plate affect the buffer-related drain lag, ... View full abstract»

• ### A 2.5 GHz Low Power, High- ${Q}$ , Reliable Design of Active Bandpass Filter

Publication Year: 2017, Page(s):229 - 244
Cited by:  Papers (1)
| |PDF (2984 KB) | HTML

In this paper, a variation-aware and reliable design of a fully integrated radio frequency (RF) bandpass filter realized using a voltage differencing transconductance amplifier is presented. The filter is characterized by its high frequency operation, low power consumption, high quality factor, and it is insensitive to process, voltage, and temperature variations. Sensitivity analysis has been per... View full abstract»

• ### Physics-of-Failure Lifetime Prediction Models for Wire Bond Interconnects in Power Electronic Modules

Publication Year: 2013, Page(s):9 - 17
Cited by:  Papers (39)
| |PDF (940 KB) | HTML

This paper presents a review of the commonly adopted physics-of-failure-based life prediction models for wire bond interconnects in power electronic modules. In the discussed models, lifetime is generally accounted for by loading temperature extremes alone. The influence of the time spent at temperature on bond wear-out behavior and damage removal phenomena resulting from thermally activated proce... View full abstract»

• ### Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Clamp Circuits

Publication Year: 2017, Page(s):577 - 584
| |PDF (2139 KB) | HTML

The power-off and power-on transient performance of power-rail electrostatic discharge (ESD) clamp circuits is investigated in this paper. In order to serve this purpose, the transient performance of a timed shutoff power-rail ESD clamp circuit in a 65-nm CMOS process is characterized by a three-terminal test method. Based on the characterization results, several insights are summarized: it is fou... View full abstract»

• ### Online Calculation of the Increase in Thermal Resistance Caused by Solder Fatigue for IGBT Modules

Publication Year: 2017, Page(s):785 - 794
| |PDF (2697 KB) | HTML

This paper addresses the catastrophic failure of power converter systems caused by the aging of the insulated-gate bipolar transistor (IGBT) module. Monitoring the aging state of IGBT in real time enables the defective module to be found and be replaced timely. Solder fatigue increasing the internal thermal resistance of the module has been identified as one of the main root causes of IGBT module ... View full abstract»

• ### Analytical Modeling of Electromigration Failure for VLSI Interconnect Tree Considering Temperature and Segment Length Effects

Publication Year: 2017, Page(s):653 - 666
| |PDF (1512 KB) | HTML

Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeli... View full abstract»

• ### Review on high-k dielectrics reliability issues

Publication Year: 2005, Page(s):5 - 19
Cited by:  Papers (307)
| |PDF (864 KB) | HTML

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO2 counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. H... View full abstract»

• ### Lifetesting GaN HEMTs With Multiple Degradation Mechanisms

Publication Year: 2015, Page(s):486 - 494
Cited by:  Papers (6)
| |PDF (1849 KB) | HTML

A technique is described, to efficiently evaluate the reliability of an RF semiconductor device when several different mechanisms contribute simultaneously to its wearout. This is of interest for present-day GaN HEMT devices because symptoms of several simultaneous degradation mechanisms have been reported widely. The technique involves first finding DC parameters that are “signaturesȁ... View full abstract»

• ### Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current

Publication Year: 2015, Page(s):156 - 162
Cited by:  Papers (4)
| |PDF (866 KB) | HTML

This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ES... View full abstract»

• ### IC Failure Analysis Due to Charged Board Events by Measurements and Modeling of Discharging Currents Through IC Pins

Publication Year: 2017, Page(s):624 - 635
| |PDF (2846 KB) | HTML

Commercial integrated circuits (ICs) were assembled on several practical printed circuit board (PCB) structures, and the discharging currents through individual pins of the IC induced by charged board events (CBE) were measured using shielded Rogowski coils. The overall CBE measurement setup was modeled and validated using circuit simulations. The structures of PCBs and a test ground plane were ef... View full abstract»

• ### Impact of Carbon Doping on Polysilicon Grain Size Distribution and Yield Enhancement for 40 nm Embedded Non-Volatile Memory Technology

Publication Year: 2018, Page(s): 1
| |PDF (938 KB)

Polysilicon (poly-Si) grain size control is a critical issue with scaling of MOS transistors in integrated circuit design, more so in embedded non-volatile memory (NVM) technology. This paper investigates an approach to suppress poly-Si grain growth under necessary additional thermal budget for 40 nm embedded NVM technology. Our studies reveal that carbon implant can suppress poly-Si grain size gr... View full abstract»

• ### Investigation of Retention Characteristics for Trap-Assisted Tunneling Mechanism in Sub 20-nm NAND Flash Memory

Publication Year: 2017, Page(s):758 - 762
| |PDF (827 KB) | HTML

In this paper, retention characteristics of the trap-assisted tunneling (TAT) mechanism are investigated in sub 20-nm NAND flash memory. Total charge loss source for the TAT mechanism (ΔVth(TAT)) becomes larger with baking temperature, while the source for the detrapping mechanism is almost constant. This temperature dependence of the TAT mechanism becomes larger as program/erase... View full abstract»

• ### Modeling the Endurance Reliability of Intradisk RAID Solutions for Mid-1X TLC NAND Flash Solid-State Drives

Publication Year: 2017, Page(s):713 - 721
| |PDF (1884 KB) | HTML

Ensuring data protection in solid state drives (SSDs) is vital in enterprise application scenario. However, as the reliability of their storage medium, namely, the NAND Flash, is decreasing at the same pace of the technology scaling, this activity is becoming nontrivial. The evaluation of different recovery strategies that employ complex error-correction codes and second-level error correction is ... View full abstract»

• ### Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

Publication Year: 2010, Page(s):418 - 426
Cited by:  Papers (67)
| |PDF (1067 KB) | HTML

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliab... View full abstract»

• ### MEMS Reliability Review

Publication Year: 2012, Page(s):482 - 493
Cited by:  Papers (54)
| |PDF (591 KB) | HTML

Microelectromechanical systems (MEMS) represents a technology that integrates miniaturized mechanical and electromechanical components (i.e., sensors and actuators) that are made using microfabrication techniques. MEMS devices have become an essential component in a wide range of applications, ranging from medical and military to consumer electronics. As MEMS technology is implemented in a growing... View full abstract»

• ### Reliability Characteristics of Ferroelectric $hbox{Si:HfO}_{2}$ Thin Films for Memory Applications

Publication Year: 2013, Page(s):93 - 97
Cited by:  Papers (39)
| |PDF (825 KB) | HTML

Reliability characteristics of ferroelectric thin films (10 nm) based on Si-doped HfO2 have been investigated with focus on potential memory applications. Extensive retention, imprint, and endurance data for this new type of ferroelectric material are presented for the first time. The variability of reliability characteristics in terms of capacitor annealing temperatures as well as exci... View full abstract»

• ### Real-Time Temperature Estimation for Power MOSFETs Considering Thermal Aging Effects

Publication Year: 2014, Page(s):220 - 228
Cited by:  Papers (36)
| |PDF (1513 KB) | HTML

This paper presents a novel real-time power-device temperature estimation method that monitors the power MOSFET's junction temperature shift arising from thermal aging effects and incorporates the updated electrothermal models of power modules into digital controllers. Currently, the real-time estimator is emerging as an important tool for active control of device junction temperature as well as o... View full abstract»

• ### Selectivity Tuning of Graphene Oxide Based Reliable Gas Sensor Devices by Tailoring the Oxygen Functional Groups: A DFT Study Based Approach

Publication Year: 2017, Page(s):738 - 745
| |PDF (1851 KB) | HTML

This paper concerns the selectivity tuning of graphene oxide based gas sensor devices, where the role of oxygen functional groups like, carboxyl, carbonyl, hydroxyl (sp2), epoxy, and hydroxyl (sp3) were investigated for physisorption of NO2, NH3, CO, and H2O using first principle calculation (density functional theory) incorporating Atomistix ... View full abstract»

• ### Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

Publication Year: 2005, Page(s):235 - 249
Cited by:  Papers (98)  |  Patents (5)
| |PDF (1016 KB) | HTML

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protect... View full abstract»

• ### Simulation Evaluation of an Implemented Set of Complementary Bulk Built-In Current Sensors With Dynamic Storage Cell

Publication Year: 2014, Page(s):255 - 261
Cited by:  Papers (15)
| |PDF (1169 KB) | HTML

This paper describes the design, the physical implementation, and the test procedure for a complementary pair of bulk built-in current sensors (Bulk-BICS) circuits, intended to detect single-event transients (SETs) induced by ionizing radiation on n- and p-type metal-oxide-semiconductor transistors. Electrical characterization of the prototype chip was performed, and the results are presented here... View full abstract»

• ### Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems

Publication Year: 2017, Page(s):490 - 506
Cited by:  Papers (1)
| |PDF (4403 KB) | HTML

This paper focuses on efficient reliability analysis methodologies applicable for beyond-5G communication systems demonstrated on prospective terahertz (THz) technologies. Recently, a lot of the research interests have grown on optoelectronic integration which requires simultaneous management of electronic and optical modules. These technologies are evolving very rapidly, providing higher complexi... View full abstract»

• ### Lateral DMOS With Partial-Resist-Implanted Drift Region for Alleviating Hot-Carrier Effect

Publication Year: 2017, Page(s):780 - 784
| |PDF (1209 KB) | HTML

Maximum operating gate voltage (Vgmax) stress is observed and confirmed as the worst hot-carrier degradation condition for the lateral double-diffused MOS (LDMOS) with multiple floating poly-gate field plates. To reduce the worst degradation, an improved N-drift region implantation method called a partial-resist-implantation is proposed for the LDMOS. It shows that the electrical fields... View full abstract»

• ### Effect of Radiation on Reliability of Through-Silicon via for 3-D Packaging Systems

Publication Year: 2017, Page(s):708 - 712
| |PDF (955 KB) | HTML

In this paper, radiation reliability of through-silicon via (TSV) was studied experimentally. Characterization of leakage current between adjacent TSVs and capacitance of an array of TSVs was used to evaluate the effects of radiation on reliability of TSVs. All samples were exposed to 60Co γ radiation with a total radiation dose of 500 Gy. It was observed that leakage current inc... View full abstract»

• ### Charge-based capacitance measurements (CBCM) on MOS devices

Publication Year: 2002, Page(s):9 - 12
Cited by:  Papers (20)
| |PDF (201 KB) | HTML

A new simple method of measuring capacitance-voltage characteristics of MOS devices is presented. Proceeding from the charge-based capacitance measurement technique suggested recently, a compact test structure with high resolution has been developed, which only requires measurement of do quantities. The method was tested on a 0.6-μm CMOS process with small and large area capacitors and compared... View full abstract»

• ### Soft-Failures Induced by System-Level ESD

Publication Year: 2017, Page(s):90 - 98
Cited by:  Papers (2)
| |PDF (1460 KB) | HTML

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply ne... View full abstract»

• ### Suppression of Row Hammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology

Publication Year: 2016, Page(s):685 - 687
Cited by:  Papers (2)
| |PDF (380 KB) | HTML

The row hammer effect has become a reliability issue that cannot be ignored in sub-30-nm dynamic random-access memory (DRAM) products because of the narrow isolation spacing between the array devices. Improving the row hammer effect via fabrication process optimization is first proposed in this paper. An additional phosphorus (P) implantation with energy and dosage modification applied in the comm... View full abstract»

• ### System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

Publication Year: 2017, Page(s):570 - 576
| |PDF (1313 KB) | HTML

This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8-μm bipolar process for TVS chips. The I-V curves of the TVS and CAN transceiv... View full abstract»

• ### Electromigration Effect on Kinetics of Cu–Sn Intermetallic Compound Growth in Lead-Free Solder Joint

Publication Year: 2017, Page(s):773 - 779
| |PDF (957 KB) | HTML

Intermetallic compounds (IMCs) growth is often accompanied by void and crack formation. It can reduce the mechanical properties and reliability of solder joints. In this paper, based on the Cu mass transport mechanisms, a theory model is established to analyze the IMC growth behaviors on Cu/Sn/Cu interconnection structures. The influence of IMC dissolution process is considered to investigate the ... View full abstract»

• ### ESD Robustness Enhancement Study of Ultra-High-Voltage JFET With Ballast Structure

Publication Year: 2017, Page(s):616 - 623
| |PDF (2847 KB) | HTML

Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current p... View full abstract»

• ### Fast-Pulsed Characterization of RF GaN HEMTs in Lifetest Systems

Publication Year: 2017, Page(s):130 - 137
Cited by:  Papers (1)
| |PDF (867 KB) | HTML

We report a new application of microsecond-pulsed current-voltage characterization of field-effect transistor (FET) devices; namely, in compact, mutlichannel DC and RF lifetest systems. This application is important for routine monitoring of trap-related signature parameters in lifetests, and is particularly useful for study of GaN high electron mobility transistors (HEMTs) due to the wide variety... View full abstract»

• ### Soft errors in advanced semiconductor devices-part I: the three radiation sources

Publication Year: 2001, Page(s):17 - 22
Cited by:  Papers (197)
| |PDF (128 KB) | HTML

In this review paper, we summarize the key distinguishing characteristics and sources of the three primary radiation mechanisms responsible for inducing soft errors in semiconductor devices and discuss methods useful for reducing the impact of the effects in final packaged parts View full abstract»

• ### Total Dose Effects On Voltage References in 130 nm CMOS Technology

Publication Year: 2017, Page(s): 1
| |PDF (1757 KB)

This work investigates the impact of Total Ionizing dose (TID) effects on the performance of CMOS voltage reference circuits. Four circuits were designed using a commercial 130 nm CMOS process and without any radiation-hardening technique. Two of the designed circuits generate the output voltage proportional to the bandgap voltage, while the other two generate the output voltage proportional to th... View full abstract»

• ### ESD Behavior of MWCNT Interconnects—Part I: Observations and Insights

Publication Year: 2017, Page(s):600 - 607
| |PDF (1910 KB) | HTML

Multiwall carbon nanotube (MWCNT)-based interconnects have been shown to outperform conventional metal interconnects. For reliable operation of such interconnects, it is imperative to evaluate their reliability at possible fatal events. Here, we report the ESD reliability of MWCNT-based interconnects. High failure current of ~10 mA and unique failure behavior involving discrete and gradual breakdo... View full abstract»

• ### Bending Performance of Flexible Organic Thin-Film Transistors with/without Encapsulation Layer

Publication Year: 2017, Page(s): 1
| |PDF (463 KB)

Flexible pentacene-based organic thin-film transistors (OTFTs) were fabricated and their performance was investigated as a function of the bending radius and the thickness of the polydimethylsiloxane (PDMS) encap-sulation layer. The TFTs were fabricated on a flexible polyimide (PI) film (film thickness: 75 μm), and encapsulated by a PDMS layer. Degradation of the device performance during a... View full abstract»

• ### A Review on the ESD Robustness of Drain-Extended MOS Devices

Publication Year: 2012, Page(s):615 - 625
Cited by:  Papers (33)
| |PDF (2457 KB) | HTML

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentar... View full abstract»

• ### Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers

Publication Year: 2015, Page(s):242 - 249
| |PDF (2178 KB) | HTML

The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circ... View full abstract»

• ### Technological Journey Towards Reliable Microheater Development for MEMS Gas Sensors: A Review

Publication Year: 2014, Page(s):589 - 599
Cited by:  Papers (11)
| |PDF (647 KB) | HTML

Micromachined silicon platforms, owing to some of its inherent advantages including miniaturized dimensions, ultralow power consumption, reduced batch fabrication cost, long-term reliability, and compatibility with standard CMOS fabrication technology, attracted the attention of solid-state gas sensor researchers, particularly since the last decade. As the semiconducting gas sensing thin film on t... View full abstract»

• ### A Review on the Reliability of GaN-Based LEDs

Publication Year: 2008, Page(s):323 - 331
Cited by:  Papers (140)
| |PDF (370 KB) | HTML

We review the degradation mechanisms that limit the reliability of GaN-based light-emitting diodes (LEDs). We propose a set of specific experiments, which is aimed at separately analyzing the degradation of the properties of the active layer, of the ohmic contacts and of the package/phosphor system. In particular, we show the following: 1) low-current density stress can determine the degradation o... View full abstract»

• ### Postvoiding Stress Evolution in Confined Metal Lines

Publication Year: 2016, Page(s):50 - 60
Cited by:  Papers (6)
| |PDF (1384 KB) | HTML

Electromigration (EM)-induced voiding is an important reliability concern in modern integrated circuits. Resistance degradation in interconnect metal lines caused by voiding was studied in this paper theoretically by solving the continuity equation describing the stress evolution caused by growing void. A rigid confinement surrounding a metal line makes inapplicable an approximation of the line ed... View full abstract»

• ### Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Publication Year: 2007, Page(s):509 - 517
Cited by:  Papers (159)
| |PDF (370 KB) | HTML

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that d... View full abstract»

• ### SRAM circuit-failure modeling and reliability simulation with SPICE

Publication Year: 2006, Page(s):235 - 246
Cited by:  Papers (18)
| |PDF (1005 KB) | HTML

Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circ... View full abstract»

• ### A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

Publication Year: 2016, Page(s):667 - 684
Cited by:  Papers (2)
| |PDF (2629 KB) | HTML

We review the Raman thermography technique, which has been developed to determine the temperature in and around the active area of semiconductor devices with submicron spatial and nanosecond temporal resolution. This is critical for the qualification of device technology, including for accelerated lifetime reliability testing and device design optimization. Its practical use is illustrated for GaN... View full abstract»

• ### Lifetime Estimation of Insulated Gate Bipolar Transistor Modules Using Two-Step Bayesian Estimation

Publication Year: 2017, Page(s):414 - 421
| |PDF (807 KB) | HTML

The reliability of the package of insulated gate bipolar transistor (IGBT) modules has been of great concern. Some fatigue-related failure mechanisms are commonly observed under power cycling conditions. An approach of a multi-step Bayesian estimation is proposed to perform lifetime estimation of IGBT modules under power cycling conditions. Lifetime estimation of a generic IGBT module under the sp... View full abstract»

## Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.