# IEEE Transactions on Device and Materials Reliability

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

Publication Year: 2008, Page(s):501 - 508
Cited by:  Papers (19)  |  Patents (7)
| | PDF (381 KB) | HTML

Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling ... View full abstract»

• ### Reliability of GaN High-Electron-Mobility Transistors: State of the Art and Perspectives

Publication Year: 2008, Page(s):332 - 343
Cited by:  Papers (286)
| | PDF (1301 KB) | HTML

Failure modes and mechanisms of AlGaN/GaN high-electron-mobility transistors are reviewed. Data from three de-accelerated tests are presented, which demonstrate a close correlation between failure modes and bias point. Maximum degradation was found in "semi-on" conditions, close to the maximum of hot-electron generation which was detected with the aid of electroluminescence (EL) measurements. This... View full abstract»

• ### Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

Publication Year: 2017, Page(s):213 - 220
| | PDF (1293 KB) | HTML

Very large-scale integrated circuit design, based on today's CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leaka... View full abstract»

• ### Capability Assessment of Inkjet Printing for Reliable RFID Applications

Publication Year: 2017, Page(s):281 - 290
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In this paper, inkjet-printed silver traces and interconnections produced with the print-on-slope technique were used in an radio-frequency identification (RFID) structure operating in the ultra-high-frequency range. Underfill material was used to attach silicon RFID chips onto flexible, 125-${\mu }\text{m}$ -thick polymer substrates. The cured underfill was also used as a sloped surface for print... View full abstract»

• ### Review on high-k dielectrics reliability issues

Publication Year: 2005, Page(s):5 - 19
Cited by:  Papers (294)
| | PDF (864 KB) | HTML

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO2 counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. H... View full abstract»

• ### Impact of X-Ray Tomography on the Reliability of Integrated Circuits

Publication Year: 2017, Page(s):59 - 68
| | PDF (1754 KB) | HTML

X-ray tomography provides 3-D information of an integrated circuit (IC) and has been utilized for counterfeit detection. Although it is a nondestructive process, electrical functionalities of IC under long time radiation has yet to be fully investigated. This paper analyzes the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3-D imaging on... View full abstract»

• ### Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

Publication Year: 2005, Page(s):235 - 249
Cited by:  Papers (88)  |  Patents (5)
| | PDF (1016 KB) | HTML

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protect... View full abstract»

Publication Year: 2005, Page(s):305 - 316
Cited by:  Papers (541)  |  Patents (6)
| | PDF (392 KB) | HTML

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creatin... View full abstract»

• ### A New SiC Trench MOSFET Structure With Protruded p-Base for Low Oxide Field and Enhanced Switching Performance

Publication Year: 2017, Page(s):432 - 437
| | PDF (1054 KB) | HTML

The high OFF-state oxide field in the SiC trench MOSFET is a threat for its long term reliability, and thus hinders the wide acceptance of the SiC trench MOSFETs. In this paper, an SiC trench MOSFET with protruded p-bases (PBMOS) is proposed, which features protruded p-bases to shield the gate oxide at the trench bottom against the high OFF-state drain voltage. Numerical device simulations based o... View full abstract»

• ### Electromigration Failure Time Model of General Circuit-Like Interconnects

Publication Year: 2017, Page(s):381 - 398
| | PDF (3700 KB) | HTML

The majority of interconnects in an integrated circuit is composed of via-terminated segments that are connected to atomic sinks or reservoirs. In this paper, we investigate electromigration failure of Cu/low-k conductors with active (current carrying) sinks and reservoirs, as well as configurations where currents flow into or out of a common via. We show that when steady-state stress profiles are... View full abstract»

• ### Reliability and Failure Analysis of UHF RFID Passive Tags Under Thermal Storage

Publication Year: 2017, Page(s):531 - 538
| | PDF (1791 KB) | HTML

This paper proposes studying the effects of thermal storage on the reliability of passive ultra-high frequency radio-frequency identification tags. Two types of tags M1 and M2 from two different manufacturers are aged under two high temperatures equal to 408 K and 433 K. Tested tags are put into thermal storage oven hang fixed terms. The performances of these tags are measured after each aging pha... View full abstract»

• ### Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Publication Year: 2017, Page(s):404 - 413
| | PDF (2231 KB) | HTML

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circ... View full abstract»

• ### Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

Publication Year: 2010, Page(s):418 - 426
Cited by:  Papers (60)
| | PDF (1067 KB) | HTML

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliab... View full abstract»

• ### Review of cooling technologies for computer products

Publication Year: 2004, Page(s):568 - 585
Cited by:  Papers (81)  |  Patents (4)
| | PDF (1976 KB) | HTML

This paper provides a broad review of the cooling technologies for computer products from desktop computers to large servers. For many years cooling technology has played a key role in enabling and facilitating the packaging and performance improvements in each new generation of computers. The role of internal and external thermal resistance in module level cooling is discussed in terms of heat re... View full abstract»

• ### Methods for Failure Analysis and Diagnosis of Millimeter-Wave System-in-Packages

Publication Year: 2017, Page(s):371 - 380
| | PDF (2348 KB) | HTML

This paper presents a sequence of affordable methods applied to diagnose a millimeter-wave system-in-package. The module used in this paper is a 60 GHz transceiver with a waveguide interface, designed to transmit 8 dBm of saturated power. It consists of a flip-chipped RFIC, a multi-layer organic substrate, a metal enclosure with a standard waveguide interface, passive components and a 30-pin conne... View full abstract»

• ### Real-Time Temperature Estimation for Power MOSFETs Considering Thermal Aging Effects

Publication Year: 2014, Page(s):220 - 228
Cited by:  Papers (28)
| | PDF (1513 KB) | HTML

This paper presents a novel real-time power-device temperature estimation method that monitors the power MOSFET's junction temperature shift arising from thermal aging effects and incorporates the updated electrothermal models of power modules into digital controllers. Currently, the real-time estimator is emerging as an important tool for active control of device junction temperature as well as o... View full abstract»

• ### Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks

Publication Year: 2009, Page(s):147 - 162
Cited by:  Papers (92)
| | PDF (1381 KB) | HTML

It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification... View full abstract»

• ### Single-Event Transient Susceptibility Analysis and Evaluation Methodology for Clock Distribution Network in the Integrated Circuit Working in Real Time

Publication Year: 2017, Page(s):539 - 548
| | PDF (2021 KB) | HTML

With technology scaling down, the clock distribution networks (CDNs) in integrated circuits (ICs) are increasingly vulnerable to the single-event transient (SET). The SET on the CDN can even lead to failure of the whole circuit. Therefore, it is important to evaluate in terms of SET susceptibility of the CDN. In this paper, a novel SET susceptibility analysis and evaluation methodology for CDN in ... View full abstract»

• ### Reliability Comparison of ZrO2-Based DRAM High-k Dielectrics Under DC and AC Stress

Publication Year: 2017, Page(s):324 - 330
| | PDF (1331 KB) | HTML

In this paper, the time dependent dielectric breakdown behavior is investigated for production type crystalline ZrO2-based thin films under dc and ac stress. Constant voltage stress measurements over six decades in time show that the voltage acceleration of time-to-breakdown follows the conventional exponential law. The effects of ac stress on time-to-breakdown are studied in detail by ... View full abstract»

• ### A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

Publication Year: 2016, Page(s):667 - 684
| | PDF (2629 KB) | HTML

We review the Raman thermography technique, which has been developed to determine the temperature in and around the active area of semiconductor devices with submicron spatial and nanosecond temporal resolution. This is critical for the qualification of device technology, including for accelerated lifetime reliability testing and device design optimization. Its practical use is illustrated for GaN... View full abstract»

• ### Analysis of the Effect of TSV-induced Stress on Devices Performance by Direct Strain and Electrical Measurements and FEA Simulations

Publication Year: 2017, Page(s): 1
| | PDF (2370 KB)

A well-documented effect of the mechanical stresses generated by 3D IC packaging on the performance of electrical circuits, in some cases leading to their parametric failure, can be controlled by means of stress assessment EDA tools. Verification and calibration of the layout engineered stress models are traditionally performed on the basis of electrical data demonstrating the stress induced chang... View full abstract»

• ### A 2.5 GHz Low Power, High- ${Q}$ , Reliable Design of Active Bandpass Filter

Publication Year: 2017, Page(s):229 - 244
| | PDF (2984 KB) | HTML

In this paper, a variation-aware and reliable design of a fully integrated radio frequency (RF) bandpass filter realized using a voltage differencing transconductance amplifier is presented. The filter is characterized by its high frequency operation, low power consumption, high quality factor, and it is insensitive to process, voltage, and temperature variations. Sensitivity analysis has been per... View full abstract»

• ### Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Clamp Circuits

Publication Year: 2017, Page(s):577 - 584
| | PDF (2139 KB) | HTML

The power-off and power-on transient performance of power-rail electrostatic discharge (ESD) clamp circuits is investigated in this paper. In order to serve this purpose, the transient performance of a timed shutoff power-rail ESD clamp circuit in a 65-nm CMOS process is characterized by a three-terminal test method. Based on the characterization results, several insights are summarized: it is fou... View full abstract»

• ### Influence of Viscoelastic Underfill on Thermal Mechanical Reliability of a 3-D-TSV Stack by Simulation

Publication Year: 2017, Page(s):340 - 348
| | PDF (2675 KB) | HTML

In this paper, we focus on how viscoelastic underfill influences the thermal mechanical reliability of a 3-D through-silicon-via (3-D-TSV) stack. The Williams-Landel-Ferry equation and relaxation of the modulus in the Prony series are used to describe the viscoelastic properties of underfill in detail. The 3-D-TSV stack consists of a four-layer die stack, a silicon interposer, a printed circuit bo... View full abstract»

• ### Optimal Design of Life Testing for High-Brightness White LEDs Using the Six Sigma DMAIC Approach

Publication Year: 2015, Page(s):576 - 587
Cited by:  Papers (1)
| | PDF (2415 KB) | HTML

Life testing is an essential reliability assessment procedure to qualify a new product or technology before being released to the market. High-brightness white light-emitting diodes (HBWLEDs) with high efficiency, environmental benefits, and high reliability have attracted increasing interest in the field of lighting systems. However, owing to the long lifetime of LEDs, traditional life testing me... View full abstract»

• ### A Nonvolatile, Low-Power, and Highly Reliable MRAM Block for Advanced Microarchitectures

Publication Year: 2017, Page(s):472 - 474
| | PDF (1031 KB) | HTML

Following the scale down of complementary metal-oxide semiconductor (CMOS) technology, radiation-induced soft errors have become a concerning issue in CMOS circuit design. Today's integrated circuits suffer from single event double node upset (SEDU) that takes place when an energetic particle strike affects two adjacent nodes. In this letter, a magnetic random access memory block capable of tolera... View full abstract»

• ### A Review on the ESD Robustness of Drain-Extended MOS Devices

Publication Year: 2012, Page(s):615 - 625
Cited by:  Papers (24)
| | PDF (2457 KB) | HTML

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentar... View full abstract»

• ### Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

Publication Year: 2017, Page(s):245 - 252
| | PDF (1657 KB) | HTML

In this paper, we investigate for the first time effect of positive (donor) and negative (acceptor) interface trap charges on the performance of proposed heterogeneous gate dielectric (HD) electrically doped tunnel field-effect transistor (EDTFET) in terms of dc, analog/RF, and linearity distortion parameters, where the HD layer is considered as a gate dielectric to improve the ON-state current an... View full abstract»

• ### Reliability Characteristics of Ferroelectric $hbox{Si:HfO}_{2}$ Thin Films for Memory Applications

Publication Year: 2013, Page(s):93 - 97
Cited by:  Papers (31)
| | PDF (825 KB) | HTML

Reliability characteristics of ferroelectric thin films (10 nm) based on Si-doped HfO2 have been investigated with focus on potential memory applications. Extensive retention, imprint, and endurance data for this new type of ferroelectric material are presented for the first time. The variability of reliability characteristics in terms of capacitor annealing temperatures as well as exci... View full abstract»

• ### High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes

Publication Year: 2017, Page(s):20 - 31
| | PDF (2323 KB) | HTML

Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlati... View full abstract»

• ### Current Status of Reliability in Extended and Beyond CMOS Devices

Publication Year: 2016, Page(s):647 - 666
Cited by:  Papers (3)
| | PDF (3090 KB) | HTML

In the history of electronics, solid-state materials replaced the vacuum parts to reduce power consumption and to obtain better reliability at a reduced cost. The size of solid-state transistors continued to reduce since its introduction, and currently, we have transistors with dimensions on the order of ~10 nm. This downscaling of transistor dimension accompanied with proportionate changes in sup... View full abstract»

• ### Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

Publication Year: 2008, Page(s):98 - 121
Cited by:  Papers (65)
| | PDF (1040 KB) | HTML

The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by... View full abstract»

• ### System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

Publication Year: 2017, Page(s):570 - 576
| | PDF (1313 KB) | HTML

This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8- ${\mu }\text{m}$ View full abstract»

• ### Characterizing Interfacial Sliding of Through-Silicon-Via by Nano-Indentation

Publication Year: 2017, Page(s):355 - 363
| | PDF (1517 KB) | HTML

In this paper, an experimental method is proposed to determine the shear sliding behavior of the interface between a copper through-silicon-via (TSV) and silicon. This interface was loaded in a nano-indentation experiment on specimens that were fabricated using focused-ion-beam milling. The elastic and plastic properties of the copper via were first characterized by micro-pillar compression experi... View full abstract»

• ### Soft errors in advanced semiconductor devices-part I: the three radiation sources

Publication Year: 2001, Page(s):17 - 22
Cited by:  Papers (187)
| | PDF (128 KB) | HTML

In this review paper, we summarize the key distinguishing characteristics and sources of the three primary radiation mechanisms responsible for inducing soft errors in semiconductor devices and discuss methods useful for reducing the impact of the effects in final packaged parts View full abstract»

• ### Effect of Body Bias on NBTI of p-MOSFETs

Publication Year: 2017, Page(s):399 - 403
| | PDF (753 KB) | HTML

The effect of the body bias on the stability of the threshold voltage of p+ polysilicon gate p-channel MOS (pMOS) transistors stressed in the on-state is investigated. Special attention is given to pMOS transistors operating at low gate overdrive and non-zero body voltage. A mixed mode of degradation, including the usual negative bias temperature instability (NBTI) and the effect of hot... View full abstract»

• ### ESD Behavior of MWCNT Interconnects - Part II: Unique Current Conduction Mechanism

Publication Year: 2017, Page(s): 1
| | PDF (1271 KB)

High current carrying capacity and superior thermal conductivity have made multiwall carbon nanotubes (MWCNTs) a material for next-generation interconnects. Its distinct electrical and thermal properties result in various physical phenomenon, interaction among which give rise to unique electro-thermal transport. The interaction aggravates in presence of high-electric fields, which generally occur ... View full abstract»

• ### Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

Publication Year: 2017, Page(s):267 - 277
| | PDF (1948 KB) | HTML

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the... View full abstract»

• ### The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

Publication Year: 2016, Page(s):610 - 616
| | PDF (1519 KB) | HTML

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (WFin_bottom), which... View full abstract»

• ### A Novel Localized-Trapped-Charge-Induced Threshold Voltage Model for Double-Fin Multi-Channel FETs (DFMcFETs)

Publication Year: 2017, Page(s):291 - 297
| | PDF (1688 KB) | HTML

With the effects of localized trapped charges on the flat-band voltage, a novel localized-trapped-charge-induced threshold voltage model for the double-fin multi-channel FET (DFMcFET) is presented based on the quasi-3-D scaling equation and minimum bottom-central potential. It is shown that the deep trench of the DFMcFET is superior to the shallow one in respect of reducing the localized-trapped-c... View full abstract»

• ### 9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue

Publication Year: 2016, Page(s):172 - 182
Cited by:  Papers (1)
| | PDF (2018 KB) | HTML

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly... View full abstract»

• ### Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Publication Year: 2007, Page(s):509 - 517
Cited by:  Papers (151)
| | PDF (370 KB) | HTML

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that d... View full abstract»

• ### Non-Uniform Aged Modules Reconfiguration for Large-Scale PV Array

Publication Year: 2017, Page(s):560 - 569
| | PDF (2273 KB) | HTML

In the past decades, a large number of photovoltaic (PV) plants have been built. Due to the minor physical differences between PV cells and the influence of environmental factors such as rains, temperature, and humidity, the aging of a PV array is often distributed unevenly within each PV module. This non-uniform aging causes further decreased output power, which is often easily observed for large... View full abstract»

• ### Mechanisms of RF Current Collapse in AlGaN–GaN High Electron Mobility Transistors

Publication Year: 2008, Page(s):240 - 247
Cited by:  Papers (51)
| | PDF (384 KB) | HTML

The physical mechanisms underlying RF current- collapse effects in AlGaN-GaN high-electron-mobility transistors are investigated by means of measurements and numerical device simulations. This paper suggests the following conditions: 1) both surface and buffer traps can contribute to RF current collapse through a similar physical mechanism involving capture and emission of electrons tunneling from... View full abstract»

• ### Soft-Failures Induced by System-Level ESD

Publication Year: 2017, Page(s):90 - 98
| | PDF (1460 KB) | HTML

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply ne... View full abstract»

• ### Fast-Pulsed Characterization of RF GaN HEMTs in Lifetest Systems

Publication Year: 2017, Page(s):130 - 137
Cited by:  Papers (1)
| | PDF (867 KB) | HTML

We report a new application of microsecond-pulsed current-voltage characterization of field-effect transistor (FET) devices; namely, in compact, mutlichannel DC and RF lifetest systems. This application is important for routine monitoring of trap-related signature parameters in lifetests, and is particularly useful for study of GaN high electron mobility transistors (HEMTs) due to the wide variety... View full abstract»

• ### Physics-of-Failure Lifetime Prediction Models for Wire Bond Interconnects in Power Electronic Modules

Publication Year: 2013, Page(s):9 - 17
Cited by:  Papers (34)
| | PDF (940 KB) | HTML

This paper presents a review of the commonly adopted physics-of-failure-based life prediction models for wire bond interconnects in power electronic modules. In the discussed models, lifetime is generally accounted for by loading temperature extremes alone. The influence of the time spent at temperature on bond wear-out behavior and damage removal phenomena resulting from thermally activated proce... View full abstract»

• ### Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Publication Year: 2004, Page(s):99 - 109
Cited by:  Papers (124)  |  Patents (7)
| | PDF (456 KB) | HTML

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specifi... View full abstract»

• ### Identifying PV Module Mismatch Faults by a Thermography-Based Temperature Distribution Analysis

Publication Year: 2014, Page(s):951 - 960
Cited by:  Papers (13)
| | PDF (1334 KB) | HTML

Photovoltaic (PV) solar power generation is proven to be effective and sustainable but is currently hampered by relatively high costs and low conversion efficiency. This paper addresses both issues by presenting a low-cost and efficient temperature distribution analysis for identifying PV module mismatch faults by thermography. Mismatch faults reduce the power output and cause potential damage to ... View full abstract»

• ### Fast-IV Measurement Investigation of the Role of TiN Gate Nitrogen Concentration on Bulk Traps in HfO2 Layer in p-MOSFETs

Publication Year: 2017, Page(s):475 - 478
| | PDF (517 KB) | HTML

This letter investigates the role of the TiN gate's nitrogen concentration on bulk traps in the HfO2 layer in p-MOSFETs using fast I -V measurement. During negative bias temperature instability, the holes trapped in the HfO2 layer will induce Vth degradation. The fast I -V double sweep confirms the holes are trapped in process-related pre-existing defects. These defects are i... View full abstract»

## Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.