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Components and Packaging Technologies, IEEE Transactions on

Popular Articles (December 2014)

Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
  • 1. Dynamic lithium-ion battery model for system simulation

    Page(s): 495 - 505
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    Presents here a complete dynamic model of a lithium ion battery that is suitable for virtual-prototyping of portable battery-powered systems. The model accounts for nonlinear equilibrium potentials, rate- and temperature-dependencies, thermal effects and response to transient power demand. The model is based on publicly available data such as the manufacturers' data sheets. The Sony US18650 is used as an example. The model output agrees both with manufacturer's data and with experimental results. The model can be easily modified to fit data from different batteries and can be extended for wide dynamic ranges of different temperatures and current rates. View full abstract»

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  • 2. Prognostics and health management of electronics

    Page(s): 222 - 229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (483 KB)  

    There has been a growing interest in monitoring the ongoing "health" of products and systems in order to predict failures and provide warning to avoid catastrophic failure. Here, health is defined as the extent of degradation or deviation from an expected normal condition. While the application of health monitoring, also referred to as prognostics, is well established for assessment of mechanical systems, this is not the case for electronic systems. However, electronic systems are integral to the functionality of most systems today, and their reliability is often critical for system reliability. This paper presents the state-of-practice and the current state-of-research in the area of electronics prognostics and health management. Four current approaches include built-in-test (BIT), use of fuses and canary devices, monitoring and reasoning of failure precursors, and modeling accumulated damage based on measured life-cycle loads. Examples are provided for these different approaches, and the implementation challenges are discussed. View full abstract»

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  • 3. Power and life extension of battery-ultracapacitor hybrids

    Page(s): 120 - 131
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    The performance of a battery-ultracapacitor hybrid power source under pulsed load conditions is analytically described using simplified models. We show that peak power can be greatly enhanced, internal losses can be considerably reduced, and that discharge life of the battery is extended. Greatest benefits are seen when the load pulse rate is higher than the system eigenfrequency and when the pulse duty is small. Actual benefits are substantial; adding a 23 F ultracapacitor bank (3 × 7 PC10 ultracapacitors) in parallel with a typical Li-ion battery of 7.2 V and 1.35 A hr capacity can boost the peak power capacity by 5 times and reduce the power loss by 74%, while minimally impacting system volume and weight, for pulsed loads of 5 A, 1 Hz repetition rate, and 10% duty View full abstract»

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  • 4. Thermal Challenges in Next-Generation Electronic Systems

    Page(s): 801 - 815
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1993 KB) |  | HTML iconHTML  

    Thermal challenges in next-generation electronic systems, as identified through panel presentations and ensuing discussions at the workshop, Thermal Challenges in Next Generation Electronic Systems, held in Santa Fe, NM, January 7-10, 2007, are summarized in this paper. Diverse topics are covered, including electrothermal and multiphysics codesign of electronics, new and nanostructured materials, high heat flux thermal management, site-specific thermal management, thermal design of next-generation data centers, thermal challenges for military, automotive, and harsh environment electronic systems, progress and challenges in software tools, and advances in measurement and characterization. Barriers to further progress in each area that require the attention of the research community are identified. View full abstract»

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  • 5. Contact resistance calculations: generalizations of Greenwood's formula including interface films

    Page(s): 50 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    The calculation of the contact resistance between two rough electrodes is a difficult task, since the contact interface comprises many spots corresponding to more or less conducting paths for the electrons. The present paper starts with an analytical formula derived by J.A. Greenwood (1966) to find the electrical resistance of a cluster of perfect circular microcontacts. It is first shown that Greenwood's formula can be used to derive known and new formulas for the constriction resistance of single spots of various shapes. Then we consider the case where the microcontacts are not perfect, and characterize each microcontact by a film resistance. To generalize Greenwood's formula, we use an intermediate expression derived by this author, and substitute for the constriction resistance term of each spot, a term comprising the constriction resistance and the film resistance. We then test the formulas proposed. In all situations the electrical contact area is modeled by means of a set of square spots. At first, we consider experimental results concerning long rectangular spots. Then, we consider numerical results concerning square ring-shaped spots. And lastly, we consider the ease where two large electrodes communicate through two concentric thin flat rings of variable conductivity. The contact resistance is then calculated using Greenwood's generalized formula and by means of the finite-element method. All tests are passed satisfactorily View full abstract»

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  • 6. Contact physics of gold microcontacts for MEMS switches

    Page(s): 357 - 364
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    This work presents a study of gold metallic contacts regarding contact resistance, heat dissipation, and surface damage in the normal-force regime of tens to hundreds of μN, which is typical of the contact forces from microactuation. The purpose of this work is to present the micromechanical switch designer with practical information on gold contact phenomena in this force regime, as most work in micrometallic contacts has focused on contact forces greater than 1 mN. Results indicate actuation forces of several hundred μN are required for reliable fully metallic contacts, with resistance and current carrying ability primarily dependent on morphology, thermal management, and nm-depth material properties of the contact electrodes View full abstract»

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  • 7. Electrical Contact Resistance Degradation of a Hot-Switched Simulated Metal MEMS Contact

    Page(s): 75 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (982 KB) |  | HTML iconHTML  

    Electrical contact resistance testing was performed by hot-switching a simulated gold-platinum metal microelectromechanical systems contact. The experimental objective was to determine the sensitivity of the contact resistance degradation to current level and environment. The contact resistance increased sharply after 100hot-switched cycles in air. Hot-switching at a reduced current and in nitrogen atmosphere curtailed contact resistance degradation by several orders of magnitude. The mechanism responsible for the resistance degradation was found to be arc-induced decomposition of adsorbed surface contaminants View full abstract»

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  • 8. Assessment of high-heat-flux thermal management schemes

    Page(s): 122 - 141
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB) |  | HTML iconHTML  

    This paper explores the recent research developments in high-heat-flux thermal management. Cooling schemes such as pool boiling, detachable heat sinks, channel flow boiling, microchannel and mini-channel heat sinks, jet-impingement, and sprays, are discussed and compared relative to heat dissipation potential, reliability, and packaging concerns. It is demonstrated that, while different cooling options can be tailored to the specific needs of individual applications, system considerations always play a paramount role in determining the most suitable cooling scheme. It is also shown that extensive fundamental electronic cooling knowledge has been amassed over the past two decades. Yet there is now a growing need for hardware innovations rather than perturbations to those fundamental studies. An example of these innovations is the cooling of military avionics, where research findings from the electronic cooling literature have made possible the development of a new generation of cooling hardware which promise order of magnitude increases in heat dissipation compared to today's cutting edge avionics cooling schemes View full abstract»

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  • 9. Optimization of plate fin heat sinks using entropy generation minimization

    Page(s): 159 - 165
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    The specification and design of heat sinks for electronic applications is not easily accomplished through the use of conventional thermal analysis tools because “optimized” geometric and boundary conditions are not known a priori. A procedure is presented that allows the simultaneous optimization of heat sink design parameters based on a minimization of the entropy generation associated with heat transfer and fluid friction. All relevant design parameters for plate fin heat sinks, including geometric parameters, heat dissipation, material properties and flow conditions can be simultaneously optimized to characterize a heat sink that minimizes entropy generation and in turn results in a minimum operating temperature. In addition, a novel approach for incorporating forced convection through the specification of a fan curve is integrated into the optimization procedure, providing a link between optimized design parameters and the system operating point. Examples are presented that demonstrate the robust nature of the model for conditions typically found in electronic applications. The model is shown to converge to a unique solution that gives the optimized design conditions for the imposed problem constraints View full abstract»

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  • 10. Thermal Resistance and Reliability of High-Power LED Packages Under WHTOL and Thermal Shock Tests

    Page(s): 738 - 746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1695 KB) |  | HTML iconHTML  

    The light emitting diode (LED) packaging problems associated with high cost, high junction temperature, low luminous efficiency, and low reliability have to be resolved before the LED gaining more market acceptance. In this paper, chip-on-plate (CoP) LED packages with and without phosphors are evaluated in terms of thermal resistance and reliability under wet and high-temperature operation life (WHTOL) and thermal shock tests. The WHTOL test is with the condition of 85°C/85%RH and 350 mA of forward current for 1008 h, while thermal shock test is with 200 cycles at temperature ranging from -40°C to 125°C. The thermal behavior of the CoP packages was analyzed by 1-D thermal resistance circuit (1-D TRC) with and without spreading angle, 3-D TRC method, and 2-D axisymmetric finite element method. The feasibility of these analyses was evaluated and discussed in detail by comparing those results with experimental measurements. The reliability results indicated that all CoP packages with phosphors in the silicone encapsulant failed after 309 h in the WHTOL test, but all those without phosphors still survived after 1008 h. The failure modes were found to be the debonding of the aluminum wire from the chip or copper pad of the substrate. However, after the aluminum wire was replaced by gold wire, all the packages with and without phosphors passed after 1008 h. For these survival packages in the WHTOL test, their thermal resistances of junction-to-air and junction-to-aluminum substrate increased by about 12 and 9°C/W, respectively. Moreover, it was also found that there is a difference of 38°C/W in the junction-to-air thermal resistances for the packages between under natural and forced convections in the chamber during the WHTOL test. This might yield the different reliability data, unless the flow conditions in the test chamber are specified in this standard test. Furthermore, all the packages with and without phosphors could pass 200- - cycles in thermal shock test, with minor changes in the thermal resistances. However, the degradation of luminous flux in the packages with phosphors was found to be greater than those without phosphors by 14% vs. 9%. View full abstract»

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  • 11. Effect of Permittivity and Permeability of a Flexible Magnetic Composite Material on the Performance and Miniaturization Capability of Planar Antennas for RFID and Wearable Wireless Applications

    Page(s): 849 - 858
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (917 KB) |  | HTML iconHTML  

    This paper is an investigation of the feasibility of applying a mechanically flexible magnetic composite material to radio frequency identification (RFID) planar antennas operating in the lower ultrahigh-frequency (UHF) spectrum (~300500 MHz). A key challenge is that the magnetic loss introduced by the magnetic composite must be sufficiently low for successful application at the targeted operating frequency. A flexible magnetic composite comprised of particles of Z-phase Co hexaferrite, also known as Co2Z, in a silicone matrix was developed. To the authors' knowledge, this is the first flexible magnetic composite demonstrated to work at these frequencies. The benchmarking structure was a quarter-wavelength microstrip patch antenna. Antennas on the developed magnetic composite and pure silicone substrates were electromagnetically modeled in Ansoft High-Frequency Sounder System full wave electromagnetic software. A prototype of the antenna on the magnetic composite was fabricated, and good agreement between the simulated and measured results was found. Comparison of the antennas on the magnetic composite versus the pure silicone substrate showed miniaturization capability of 2.4 times and performance differences of increased bandwidth and reduced gain, both of which were attributed in part to the increase in the dielectric and magnetic losses. A key finding of this paper is that a small amount of permeability (mur~2.5) can provide a substantial capability for miniaturization, while sufficiently low-magnetic loss can be introduced for successful application at the targeted operating frequency. This magnetic composite shows the capability to fulfill this balance and to be a feasible option for RFID, flexible wearable, and conformal applications in the lower UHF spectrum. View full abstract»

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  • 12. Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area ({>}100~{\rm mm}^{2}) Chips

    Page(s): 98 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1680 KB) |  | HTML iconHTML  

    A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125??C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275??C with the sintered joints having the melting temperature of silver at 961??C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications. View full abstract»

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  • 13. Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

    Page(s): 589 - 593
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1161 KB) |  | HTML iconHTML  

    A nanoscale silver paste containing 30-nm silver particles that can be sintered at 280degC was made for interconnecting semiconductor devices. Sintering of the paste produced a microstructure containing micrometer-size porosity and a relative density of around 80%. Electrical and thermal conductivities of around 2.6times105 (Omegamiddotcm)-1 and 2.4W/K-cm, respectively, were obtained, which are much higher than those of the solder alloys that are currently used for die attachment and/or flip-chip interconnection of power semiconductor devices. The sintered porous silver had an apparent elastic modulus of about 9GPa, which is substantially lower than that of bulk silver, as well as most solder materials. The lower elastic modulus of the porous silver may be beneficial in achieving a more reliable joint between the device and substrate because of increased compliance that can better accommodate stress arising from thermal expansion mismatch View full abstract»

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  • 14. Effect of UV/ozone treatment on surface tension and adhesion in electronic packaging

    Page(s): 43 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    Surface tension of material surfaces and interfaces is an important parameter that affects wetting and adhesion. Surface tension can be divided into three components: Lifshitz-van der Waals component, acid component, and base component. In this study, the three-liquid-probe method was used to investigate the surface tension and its three components of various surfaces of electronic packaging materials: benzocyclobutene (BCB) passivation, FR-4 board, polyimide board, and alumina board. When UV/ozone was employed to treat the surfaces, the surface tension increased, and the base component increased the most. The change in surface tension due to UV/O3 treatment decayed with time after the treatment. The difference in surface tension between untreated and treated surface became smaller with the increase of time after UV/O3 treatment. Different substrates showed different rate of decay in surface tension change. Among the surfaces studied, BCB passivation showed the fastest decay after treatment, while alumina showed the slowest decay. The contact angles of several liquid underfill materials on BCB passivation and their surface tension before and after curing were also measured. It was found that the wetting was not the controlling factor in adhesion of the system investigated View full abstract»

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  • 15. Optimization of Piezoelectric Oscillating Fan-Cooled Heat Sinks for Electronics Cooling

    Page(s): 25 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1517 KB) |  | HTML iconHTML  

    Piezoelectric fans have been investigated for electronics cooling over the last decade. The primary usage or method has been to place the vibrating fan near the surface to be cooled. The piezofan used in the current study is composed of a piezo actuator attached to a flexible metal beam. It is operated at up to 120-VAC and at 60 Hz. While most of the research in the literature focused on cooling bare surfaces, larger heat transfer rates are of interest in the present study. A system of piezoelectric fans and a heat sink is presented as a more efficient method of system cooling with these fans. In this paper, a heat sink and piezoelectric fan system demonstrated a cooling capability of 1 C/W over an area of about 75 cm2 where electronic assemblies can be mounted. The heat sink not only provides surface area, but also flow shaping for the unusual 3-D flow field of the fans. A volumetric coefficient of performance (COPv) is proposed, which allows a piezofan and heat sink system volume to be compared against the heat dissipating capacity of a similar heat sink of the same volume for natural convection. A piezofan system is shown to have a COPv of five times that of a typical natural-convection solution. The paper will further discuss the effect of nozzles in flow shaping obtained via experimental and computational studies. A 3-D flow field of the proposed cooling scheme with a piezofan is obtained via a flow visualization method. Velocities at the heat sink in the order of 1.5 m/s were achieved through this critical shaping. Finally, the overall system characterization to different heat loads and fan amplitudes will be discussed. View full abstract»

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  • 16. Development of High-Performance Optical Silicone for the Packaging of High-Power LEDs

    Page(s): 761 - 766
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (737 KB) |  | HTML iconHTML  

    Silicone materials with a relatively high-refractive index have been introduced for the encapsulation of high-power light-emitting diodes (LEDs), and LEDs with relatively short wavelengths. However, most of those existing silicone encapsulants still suffer from thermal and radiation induced degradations and thus lead to reliability issues and a shorten lifetime. A new high-performance silicone has been developed and its performance is compared with other commercial silicone and optical grade epoxy in high-power white LEDs. The new materials had been found to suffer less loss in the lumen output during the aging test and high-temperature/high-humidity test, as well as the Joint Electron Devices Engineering Council (JEDEC) reliability test. It is concluded that this material is excellent for the packaging of high-power white LEDs and high-power colored LEDs, because of its ability in maintaining high-transparency and great radiation/thermal resistance. View full abstract»

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  • 17. Thermal cycling analysis of flip-chip solder joint reliability

    Page(s): 705 - 712
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (182 KB) |  | HTML iconHTML  

    The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported View full abstract»

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  • 18. Dense Vertically Aligned Multiwalled Carbon Nanotube Arrays as Thermal Interface Materials

    Page(s): 92 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1583 KB) |  | HTML iconHTML  

    Carbon nanotube (CNT) arrays are being considered as thermal interface materials (TIMs). Using a phase sensitive transient thermo-reflectance technique, we measure the thermal conductance of the two interfaces on each side of a vertically aligned CNT array as well as the CNT array itself. We show that the physically bonded interface by van der Waals adhesion has a conductance ~105W/m2K and is the dominant resistance. We also demonstrate that by bonding the free-end CNT tips to a target surface with the help of a thin layer of indium weld, the conductance can be increased to ~106W/m2K making it attractive as a TIM View full abstract»

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  • 19. Electrical contact resistance: properties of stationary interfaces

    Page(s): 85 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    The paper reviews the dependence of electrical constriction resistance on the shape and dimensions of α-spots and on the magnitude of the mechanical contact load. The range of validity of the classical voltage-temperature relation for electrical contacts is also examined. The paper describes experimental evidence of breakdown of the classical electrical contact theory when α-spots become too small. One of the interesting and useful properties of relatively small α-spots is that they are subject to large surface stresses. These stresses induce α-spot growth View full abstract»

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  • 20. Feasibility of an Integrated Self Biased Coplanar Isolator With Barium Ferrite Films

    Page(s): 411 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (815 KB) |  | HTML iconHTML  

    The development of passive devices using a ferrite is a major focus of current research for electronic applications in the microwave range (circulators and isolators). Hexagonal ferrite, such as barium ferrite (BaFe12O19 or BaM), which has a large resistivity and high permeability at high frequencies are indeed of great interest for microwave device applications. In this work we developed an integrated and self-biased coplanar isolator using BaM sputtered films. BaM films, 1-36 mum thick, were deposited under optimized conditions by radio frequency magnetron sputtering on alumina substrates. The films were crystallized using a 800degC thermal annealing. Isolators were then realized using patterning of coplanar waveguides (CPW) with standard lift-off technique. The slots and the central width were 300 mum wide and gold was used for the conductor lines. We evaluated the influence of various parameters on the device performances: the magnetic film's thickness, the positioning of the magnetic film (CPW deposited onto the magnetic film or directly on the substrate), the CPW metallic thickness and the polarizing field. As standard design, the CPW were deposited on the top of the magnetic film. At the remanent magnetization (no polarizing field applied), the transmission coefficients then showed a non reciprocal effect, which reached 5.4 dB per cm of line length at 50 GHz for a 26.5 mum thick BaM film. Both the insertion losses and the non-reciprocal effect measured increased with the magnetic film thickness with a saturation effect. In the second design where the CPW is deposited directly on the substrate after a selective etching of the BaM film, we measured that the non reciprocal effect reached higher values for lower BaM thicknesses than for the first design and that the insertion losses also decreased. The interaction between the field lines created by the conductors and the magnetic film was indeed favored in the second case. Finally, we show - the tunability of the isolator with the polarizing field. View full abstract»

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  • 21. Mechanics-based solutions to RF MEMS switch stiction problem

    Page(s): 560 - 567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    RF micro-electro-mechanical systems (MEMS) switches are an attractive solution to switch antenna bands and transmit/receive switching for future multiband, high bandwidth cell phones. However, Stiction is a major concern for resistive switches with metal-to-metal contact. An iterative-coupled electrostatic-structural analysis is utilized to evaluate the effect of design parameters on restoring force of MEMS switches. Parameters including metal thickness, dielectric thickness, beam-to-ground gap height, metal and dielectric width, and cantilever beam length can be evaluated. The electrostatic force is first calculated based on the electrical field component. A structural analysis is then performed to determine the cantilever beam deflection due to the electrostatic force. A unique integrated empirical-numerical method is used to quantitatively determine the stiction force based on measured actuation voltages for real devices. The analysis can provide quick evaluation and screenings of proposed designs to determine if their actuation voltage falls in the acceptable range. Simulation prediction agrees very well with test measurements. Although increasing cantilever thickness and shortening cantilever length both increase restoring force, the actuation voltage will increase significantly as a result. The most favorable modification is to increase the electrode area. A short and wide structure with a large area can increase restoring force while maintaining low actuation voltage. Compared to similar bi-layer designs, sandwich designs can be actuated at further reduced voltages without changing the beam restoring force. In addition, the sandwich structure, being thermal-stress-balanced, is less sensitive to temperature excursion. With the properly selected design parameters, the new designs will be able to achieve the break away restoring force of the original design at much lower actuation voltages. Switches with good electrical as well as mechanical performances have been successfully fabricated. View full abstract»

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  • 22. Shape Optimization of Micro-Channel Heat Sink for Micro-Electronic Cooling

    Page(s): 322 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (725 KB) |  | HTML iconHTML  

    A numerical investigation of 3D fluid flow and heat transfer in a rectangular micro-channel has been carried out using water as a cooling fluid in a silicon substrate. Navier-Stokes and energy equations for laminar flow and conjugate heat transfer are solved using a finite volume solver. Solutions are first carefully validated with available analytical and experimental results; the shape of the micro-channel is then optimized using surrogate methods. Ratios of the width of the micro-channel to the depth and the width of the fin to the depth are selected as design variables. Design points are selected through a four-level full factorial design. A single objective function thermal resistance, formulated using pumping power as a constraint, is optimized. Mass flow rate is adjusted by the constant pumping power constraint. Response surface approximation, kriging, and radial basis neural network methods are applied to construct surrogates and the optimum point is searched by sequential quadratic programming. View full abstract»

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  • 23. Effect of PCB Surface Modifications on the EMC-to-PCB Adhesion in Electronic Packages

    Page(s): 498 - 508
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9014 KB) |  | HTML iconHTML  

    The characteristics of interfacial adhesion between epoxy molding compound (EMC) and printed circuit board (PCB) were investigated. The surface conditions of solder resist (SR) layers, which were used as an outer skin of PCB, were varied within the range that would be encountered in the manufacturing process and reliability test conditions. First, the number of times of plasma treatment on the SR surfaces and the delay time prior to EMC molding on them were considered to examine the surface cleaning process and the aging effect, respectively, on adhesion. Second, moisture on the surfaces of PCB prior to EMC molding and moisture absorption and desorption at the interface were considered to investigate the environmental effect on adhesion. An unsymmetric double cantilever beam test method was devised by modifying the conventional symmetrical double cantilever beam. As a result, the phase angle of fracture could be controlled to achieve stable crack propagation along the desired interface, which enabled valid adhesion energy to be measured. The adhesion energy increased with plasma treatment by over 50%, from 55 to 86 J/m2. The improved adhesion was attributed to the increased the polar groups on the SR surface due to plasma treatment, which helped enhanced chemical bonding between the EMC resin and the SR resin. However, excessive plasma was counterproductive as it weakened the SR surface and caused cohesive crack propagation to occur within the SR layer. Adhesion remained nearly constant for delay time up to several hours between plasma treatment and EMC molding. However, small degradation of adhesion was observed when the delay time was extended to 12 h. Moisture on and in the SR material before EMC molding had a significant effect on adhesion. Absorbed moisture at the interface decreased the adhesion. However, when the moisture was baked out, adhesion was recovered almost to the original reference. View full abstract»

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  • 24. Design optimization of an integrated liquid-cooled IGBT power module using CFD technique

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB)  

    This paper presents a novel approach to optimize pin array design of an integrated, liquid-cooled, insulated gate bipolar transistor (IGBT) power module. With the aid of a computational fluid dynamics (CFD) code, the fluid field and heat transfer inside the module were analyzed, and several design options on pin arrays were examined. For IGBT die circuitry, the uniformity of temperature distribution among dies is as critical as the magnitude of the die temperature. A noticeable variation in temperature among dies can accelerate the thermal runaway and reduce the reliability of the devices. With geometrically-optimized-pin designs located both upstream and downstream of the channel, a total power dissipation of 1200 W was achieved. The maximum junction temperature was maintained at 100°C and the maximum variation among dies was controlled within 1°C. The results from this study indicated that the device junction temperatures were not only reduced in magnitude but were equalized as well. In addition, the maximum power dissipation of the module was enhanced. Comparison with other direct- (pool boiling) and indirect- (cold plate) liquid cooling techniques was also discussed View full abstract»

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  • 25. Carbon nanotube applications in microelectronics

    Page(s): 629 - 634
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1728 KB)  

    The extraordinary characteristics of carbon nanotubes make them a promising candidate for applications in microelectronics. Catalyst-mediated chemical vapor deposition growth is very well suited for selective in-situ growth of nanotubes compatible with the requirements of microelectronics technology. This deposition method can be exploited for carbon nanotube vias. Semiconducting single-walled tubes can be successfully operated as carbon nanotube field effect transistors (CNTFET). A simulation of an ideal CNTFET is presented and compared with the requirements of the ITRS roadmap. Finally, we compare an upgraded CNTFET with the most advanced silicon metal oxide semiconductor field effect transistors and discuss integration issues. View full abstract»

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  • 26. Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

    Page(s): 309 - 316
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (523 KB) |  | HTML iconHTML  

    During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently. The result is open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials. In this paper, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. A set of different layout patterns of bond pads has been drawn and fabricated in a 0.6-μm single-poly triple-metal CMOS process for investigation by the bond wire reliability tests, the ball shear test and the wire pull test. By implementing effective layout patterns on bond pads in packaged IC products, not only the bond wire reliability can be improved, but also the bond pad capacitance can be reduced for high frequency application. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes View full abstract»

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  • 27. High-Density Embedded Deep Trench Capacitors in Silicon With Enhanced Breakdown Voltage

    Page(s): 808 - 815
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    This paper reports on the design, implementation, and characterization of high-density trench-refilled capacitors in complementary metal-oxide-semiconductor (CMOS) grade silicon (1-10 Omegacm). High aspect ratio trench-refilled capacitors offer a capacitance density improvement of three orders of magnitude compared to thin-film capacitors with the same die area and dielectric thickness. Also, dielectric materials such as low-pressure chemical vapor deposition (LPCVD) silicon oxide and silicon nitride are utilized to enhance the breakdown voltage of these devices. The high aspect ratio polysilicon and single crystal silicon process was utilized to implement these capacitors, giving a gap aspect ratio of . This ultrahigh vertical capacitance area achieves an ultralarge capacitance density without requiring thin-or high-k dielectric material. High-value capacitors of values ranging from 40 nF to 4 muF with capacitance density of 58 (nF/mm 2) were implemented in silicon as arrays of 170 mum-deep trenches. LPCVD silicon dioxide and silicon nitride were employed as dielectric materials to provide robust deposition inside the high aspect ratio trenches. Trench-refilled capacitors show quality factors (Q) of 230 and 8, respectively, at 45 nF and 4 muF capacitances. The breakdown voltage in trench-refilled capacitors with 35 nm-thick Si3N4 is recorded to be as high as 17-V, which is ~4x to 10x larger than that of BaTiO3 and PbZrxTi1 - xO3 (PZT) thin-film capacitors with the same dielectric thickness. Furthermore, the capacitances were measured over a temperature range of 25 to 155degC, showing less than 1.8% variation in 45 nF devices. This implies that trench-refilled capacitors are free from the very strong temperature sensitivity exhibited by most high-k materials. View full abstract»

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  • 28. Effects of Cu/Al intermetallic compound (IMC) on copper wire and aluminum pad bondability

    Page(s): 367 - 374
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    Copper wire bonding is an alternative interconnection technology that serves as a viable, and cost saving alternative to gold wire bonding. Its excellent mechanical and electrical characteristics attract the high-speed, power management devices and fine-pitch applications. Copper wire bonding can be a potentially alternative interconnection technology along with flip chip interconnection. However, the growth of Cu/Al intermetallic compound (IMC) at the copper wire and aluminum interface can induce a mechanical failure and increase a potential contact resistance. In this study, the copper wire bonded chip samples were annealed at the temperature range from 150°C to 300°C for 2 to 250 h, respectively. The formation of Cu/Al IMC was observed and the activation energy of Cu/Al IMC growth was obtained from an Arrhenius plot (ln (growth rate) versus 1/T). The obtained activation energy was 26Kcal/mol and the behavior of IMC growth was very sensitive to the annealing temperature. To investigate the effects of IMC formation on the copper wire bondability on Al pad, ball shear tests were performed on annealed samples. For as-bonded samples, ball shear strength ranged from 240-260gf, and ball shear strength changed as a function of annealing times. For annealed samples, fracture mode changed from adhesive failure at Cu/Al interface to IMC layer or Cu wire itself. The IMC growth and the diffusion rate of aluminum and copper were closely related to failure mode changes. Micro-XRD was performed on fractured pads and balls to identify the phases of IMC and their effects on the ball bonding strength. From XRD results, it was confirmed that the major IMC was γ-Cu9Al4 and it provided a strong bondability. View full abstract»

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  • 29. Critical Review of the Engelmaier Model for Solder Joint Creep Fatigue Reliability

    Page(s): 693 - 700
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    A solder interconnect fatigue life model was developed by Werner Engelmaier in the early 1980s as an improvement upon the inelastic strain range-based Coffin-Manson model. As developed, the model provides a first-order estimate of cycles to failure for SnPb solder interconnects under power and thermal cycles. While the model has been widely adopted for SnPb solder joint reliability prediction, many issues that arise from simplifications in formulating input model parameters as well as from the complex physics of solder degradation challenge the model's ability to accurately estimate cycles to failure. Deficiencies with the model have been reported by a number of researchers. This paper reviews and summarizes the major issues with the Engelmaier model in its applicability to predict solder joint thermal fatigue life. View full abstract»

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  • 30. Scaling and Optimization of Gravure-Printed Silver Nanoparticle Lines for Printed Electronics

    Page(s): 105 - 114
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    Printed electronics promises to enable new applications such as RFID tags, displays and various types of sensors. Critical to the development of printed electronics is the establishment of a manufacturable printing technique with high resolution and throughput. Gravure is a high-speed roll-to-roll printing technique that has many of the characteristics necessary for a viable printed electronics process. We present the first systematic study on the scaling and optimization of conductive lines for printed electronics, especially with high viscosity nanoparticle inks. We demonstrate gravure-printed nanoparticle lines, which are potentially suitable for use in thin-film transistor (TFT) based circuits as well as passive components. We present several trends observed by varying cell and ink parameters, and compare two different techniques for printing lines. We examine current limits to scaling printed lines and demonstrate the potential viability and scalability of gravure for printed electronics. View full abstract»

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  • 31. Studies on Optical Consistency of White LEDs Affected by Phosphor Thickness and Concentration Using Optical Simulation

    Page(s): 680 - 687
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    Effects of variations of yttrium aluminum garnet:Ce phosphor thickness and concentration on optical consistency of produced white light-emitting diodes (LEDs) including the consistency of brightness and light colors were studied by optical simulation. Five packaging methods with different phosphor locations were compared. Optical models of LED chip and the phosphor were presented and a Monte Carlo ray-tracing simulation procedure was developed. Both color binning and brightness level were used to sort the simulated LEDs to evaluate their optical consistency. Results revealed that the optical consistency of white LEDs strongly depends on how the phosphor thickness and the concentration vary. To obtain desired color binning, conformal phosphor coating is not a favorable packaging method due to its low brightness level and poor brightness consistency by large shifts of the brightness level as the phosphor thickness and concentration varying. Planar remoter phosphor improves the brightness level and its consistency, but realization of high color consistency becomes more difficult due to its smaller variation ranges of the phosphor thickness and concentration. Hemispherical remoter phosphor can fulfill the requirements of both high color consistency and high brightness consistency due to its capability of larger variation ranges of the phosphor thickness and concentration. By applying this method with thick phosphor thickness or high phosphor concentration, this method can be a promising packaging method for the low cost production. View full abstract»

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  • 32. On The Problem of Using Guard Traces for High Frequency Differential Lines Crosstalk Reduction

    Page(s): 67 - 74
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    In this paper, the problem of using guard traces for reducing crosstalk between differential transmission line pairs is investigated, both experimentally and by full-wave electromagnetic (EM) simulations. Different cases of differential lines crosstalk are treated with and without guard trace separation between the differential line pairs. Coated microstrip printed circuit board test structures including thru-reflect-line calibration standards are designed and fabricated on a high frequency laminate material, allowing direct measurement of crosstalk between adjacent differential line pairs in the absence and in the presence of guard traces stitched with vias of regular spacing. The test structures are characterized with mixed-mode scattering parameters using a physical layer test system. Different configurations (of differential line pairs) without guard trace, with floating guard traces (which are terminated and nonterminated) and with a solid guard trace separation are investigated using a High Frequency Structure Simulator (a commercial full-wave 3-D EM simulation tool). The experimental data are compared with the simulation results, and some conclusions and guidelines on the effect of guard traces for alleviating crosstalk between differential transmission lines are presented View full abstract»

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  • 33. Experimental optimization of confined air jet impingement on a pin fin heat sink

    Page(s): 399 - 404
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    A variety of nozzle configurations were tested to characterize and optimize the performance of confined impinging air jets used in conjunction with a pin-fin heat sink. Four single nozzles of different diameters and two multiple-nozzle arrays were studied at a fixed nozzle-to-target spacing, for different turbulent Reynolds numbers (5000⩽Re⩽20000). Variations in the output power level of the heat source and nozzle-to-target spacing were found to have only modest effects on heat transfer at a fixed Reynolds number. Enhancement factors were computed for the heat sink relative to a bare surface, and were in the range of 2.8-9.7, with the largest value being obtained for the largest single nozzle (12.7 mm diameter). Average heat transfer coefficients and thermal resistance values are reported for the heat sink as a function of Reynolds number, air flow rate, pumping power, and pressure drop, to aid in optimizing the jet impingement configuration for given design constraints View full abstract»

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  • 34. A review of selected thermal management solutions for military electronic systems

    Page(s): 26 - 39
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    Thermal management of electronics is vital to the successful design, manufacture, and tactical operation of a variety of military electronic systems. Designs employ all modes of heat transfer including: conduction, natural and forced convection, aerodynamic heating, radiation, and two-phase heat transfer. A variety of heat sinks and heat exchange devices are employed, including the use of cold plates, electronic chassis coldwalls, compact heat exchangers, air-cycle and vapor-cycle refrigeration systems, phase change materials, thermoelectric devices, and heat pipes. This paper describes several military electronic systems on a variety of platforms and discusses the thermal management issues involved in the design of the thermal control systems. Specific examples are employed in the paper to emphasize the variety of thermal management problems encountered and the solution techniques employed. View full abstract»

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  • 35. Thermal management strategies for high power semiconductor pump lasers

    Page(s): 268 - 276
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    Semiconductor pump lasers are an important component in erbium-doped fiber amplifiers and Raman amplifiers. Thermal management has become one of the major obstacles of pump laser development. Understanding of the thermal behavior of high-power laser packages is crucial to the thermal design and optimization of pump lasers. In this paper, we report on the thermal characteristics of a high-power pump laser and discuss the issues associated with heat dissipation. The thermal management of high-power pump laser modules mainly consists of three aspects. One is the thermal resistance reduction which reduces bulk temperature rise in the laser diode chip. The second is facet temperature control, and the third is the thermoelectric cooler (TEC) coefficient of performance improvement. In this paper, the approaches to reduce thermal resistance and facet temperature at the chip level and package level will be reviewed, and the thermal design and optimization of the package assembly to improve the TEC coefficient of performance will be discussed. The thermal resistance of a pump laser could be reduced up to 40% by the proper design of the laser chip and epi-down bonding. An unpumped window design in the pump laser diode is proven to be very effective in reducing the facet temperature and increasing the catastrophic optical mirror damage level. Assembly and package optimization can provide more uniform temperature distribution on TEC cold plate which is critical in improving the TEC coefficient of performance View full abstract»

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  • 36. Reliability analysis and design for the fine-pitch flip chip BGA packaging

    Page(s): 684 - 693
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    The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package. View full abstract»

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  • 37. Electrical breakdown in atmospheric air between closely spaced (0.2 μm-40 μm) electrical contacts

    Page(s): 390 - 396
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    The increasing importance of electrical contacts in air with micrometer spacing prompted recent experiments on the electrical breakdown behavior of these gaps. The electrical field between the contacts used in one of the experiments was analyzed using finite element analysis to model the electric field. The experimental data on the electrical breakdown voltage could be divided into three regions as a function of the gap spacing. First, at close gap spacing (≤4 μm) both the breakdown voltages as well as the electrical fields at the cathode were similar to values measured during the breakdown of vacuum gaps of less than 200 μm. Second, at larger gaps (>6 μm) the breakdown voltages followed Paschen's curve for the Townsend electron avalanche process in air. Finally, in between these two regions the breakdown values were below the expected values for purely vacuum breakdown or purely Townsend breakdown. The breakdown phenomena have been discussed in terms of field emission of electrons from the cathode and their effect on initiating the observed breakdown regimes. View full abstract»

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  • 38. Characterization of compact heat sink models in natural convection

    Page(s): 78 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (345 KB) |  | HTML iconHTML  

    In this study, an approximate analytical-numerical procedure is used to model natural convection cooling of heat sinks using electronics cooling software. The analysis evolves in two stages: a numerical simulation of the detailed heat sink, and a simulation of a compact model that exhibits similar thermal and flow resistance characteristics to those of the actual heat sink. From the analysis, the thermal resistance of the heat sink is evaluated. Subsequently, the effective thermal conductivity that must be assigned to the compact heat sink is determined using the Nusselt number correlation for free convection over a vertical plate. Due to the algebraic form of the Nusselt number correlation, the effective thermal conductivity is determined in an iterative fashion. The purpose of a compact heat sink is to reduce computational effort while retaining a desired level of accuracy. In this article, the compact modeling scheme is first applied to either an extruded or a pin-fin heat sink in order to validate the procedure under laminar conditions. Subsequently, the same approach is applied to a multichip system consisting of a set of pin-fin heat sinks placed in series. At both individual and system-level models, it is found that the compact approach results in substantial savings in mesh size and computing time. These savings are accompanied by a small acceptable error that is less than 10% relative to the detailed model predictions View full abstract»

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  • 39. A novel hybrid heat sink using phase change materials for transient thermal management of electronics

    Page(s): 281 - 289
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    A hybrid heat sink concept which combines passive and active cooling approaches is proposed. The hybrid heat sink is essentially a plate fin heat sink with the tip immersed in a phase change material (PCM). The exposed area of the fins dissipates heat during periods when high convective cooling is available. When the air cooling is reduced, the heat is absorbed by the PCM. The governing conservation equations are solved using a finite-volume method on orthogonal, rectangular grids. An enthalpy method is used for modeling the melting/re-solidification phenomena. Results from the analysis elucidate the thermal performance of these hybrid heat sinks. The improved performance of the hybrid heat sink compared to a finned heat sink (without a PCM) under identical conditions, is quantified. In order to reduce the computational time and aid in preliminary design, a one-dimensional fin equation is formulated which accounts for the simultaneous convective heat transfer from the finned surface and melting of the PCM at the tip. The influence of the location, amount, and type of PCM, as well as the fin thickness on the thermal performance of the hybrid heat sink is investigated. Simple guidelines are developed for preliminary design of these heat sinks. View full abstract»

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  • 40. Printed organic transistors for ultra-low-cost RFID applications

    Page(s): 742 - 747
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1088 KB) |  | HTML iconHTML  

    Printed electronics provides a potential pathway toward the realization of ultra-low-cost radio frequency identification (RFID) tags for item-level tracking of consumer goods. Here, we report on our progress in developing materials and processes for the realization of printed transistors for low-cost RFID applications. Using inkjet printing of novel conductors, dielectrics, and organic semiconductors, we have realized printed transistors with mobilities >10-1cm2/V-s. AC performance of these devices is adequate for 135-kHz RFID, and, with further optimization, 13.56-MHz RFID appears to be within reach. We review the performance of these devices, and discuss optimization strategies for achieving the ultimate performance goals requisite for realizing ultra-low-cost printed RFID. View full abstract»

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  • 41. Capacitive Pressure Sensor With Very Large Dynamic Range

    Page(s): 79 - 83
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    A new capacitive pressure sensor with very large dynamic range is introduced. The sensor is based on a new technique for substantially changing the surface area of the electrodes, rather than the inter-electrode spacing as commonly done at the present. The prototype device has demonstrated a change in capacitance of approximately 2500 pF over a pressure range of 10 kPa. View full abstract»

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  • 42. Enhanced thermal contact conductance using carbon nanotube array interfaces

    Page(s): 261 - 267
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1838 KB) |  | HTML iconHTML  

    Heat-conduction interfaces that employ carbon nanotube (CNT) arrays have been fabricated and studied experimentally using a reference calorimeter testing rig in a vacuum environment with infrared temperature measurements. Arrays of multiwalled CNTs are grown directly on silicon substrates with microwave plasma-enhanced chemical vapor deposition. Iron and nickel were used as CNT catalysts. CNT arrays grown under different synthesis conditions exhibit different pressure-contact conductance characteristics. The thermal contact resistance of CNTs with a copper interface exhibits promising results with a minimum value of 19.8mm2K/W at a pressure of 0.445MPa View full abstract»

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  • 43. Thermal management of BioMEMS: temperature control for ceramic-based PCR and DNA detection devices

    Page(s): 309 - 316
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    Integrated microfluidic devices for amplification and detection of biological samples that employ closed-loop temperature monitoring and control have been demonstrated within a multilayer low temperature co-fired ceramics (LTCC) platform. Devices designed within this platform demonstrate a high level of integration including integrated microfluidic channels, thick-film screen-printed Ag-Pd heaters, surface mounted temperature sensors, and air-gaps for thermal isolation. In addition, thermal-fluidic finite element models have been developed using CFDRC ACE+ software which allows for optimization of such parameters as heater input power, fluid flow rate, sensor placement, and air-gap size and placement. Two examples of devices that make use of these concepts are provided. The first is a continuous flow polymerase chain reaction (PCR) device that requires three thermally isolated zones of 94°C, 65°C, and 72°C, and the second is an electronic DNA detection chip which requires hybridization at 35°C. Both devices contain integrated heaters and surface mount silicon transistors which function as temperature sensors. Closed loop feedback control is provided by an external PI controller that monitors the temperature dependant I-V relationship of the sensor and adjusts heater power accordingly. Experimental data confirms that better than ±0.5°C can be maintained for these devices irrespective of changing ambient conditions. In addition, good matching with model predictions has been achieved, thus providing a powerful design tool for thermal-fluidic microsystems. View full abstract»

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  • 44. Four decades of research on thermal contact, gap, and joint resistance in microelectronics

    Page(s): 182 - 206
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1192 KB) |  | HTML iconHTML  

    The Keynote Paper reviews and highlights over 40 years of research on solutions for steady-state and transient thermal constriction and spreading resistances, and thermomechanical models for contact, gap and joint resistances of joints formed by conforming rough surfaces, nonconforming smooth surfaces, and nonconforming rough surfaces. Microgap and macrogap thermal resistance and conductance models are reviewed, and important relations and correlation equations are presented. Contact microhardness, determined by Vickers indenters, are correlated and incorporated into the contact model for conforming rough surfaces. Microhardness parameters are correlated with Brinell hardness values. Elastoplastic contact models for joints formed by smooth sphere-smooth flat and conforming rough surfaces are presented. A simple thermomechanical model for microgaps occupied by oil, grease, grease filled with solid particles, and phase change materials such as paraffins is reviewed, and good agreement with recently published data is noted. View full abstract»

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  • 45. Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits

    Page(s): 56 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a sig- - nificant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools. View full abstract»

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  • 46. Miniature loop heat pipes-a promising means for cooling electronics

    Page(s): 290 - 296
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    Loop heat pipes (LHPs) are highly efficient heat-transfer devices, which have considerable advantages over conventional heat pipes. Currently, miniature LHPs (MLHPs) with masses ranging from 10-20 g and ammonia and water as working fluids have been developed and tested. The MLHPs are capable of transferring heat loads of 100-200 W for distances up to 300 mm in the temperature range 50-100°C at any orientation in 1-g conditions. The thermal resistance for these conditions are in the range from 0.1 to 0.2 K/W. The devices possess mechanical flexibility and are adaptable to different conditions of location and operation. Such characteristics of MLHPs open numerous prospects for use in cooling systems of electronics and computer systems. View full abstract»

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  • 47. Influence of Sn Grain Size and Orientation on the Thermomechanical Response and Reliability of Pb-free Solder Joints

    Page(s): 370 - 381
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    The size and crystal orientation of Sn grains in Pb-free, near eutectic Sn-Ag-Cu solder joints were examined. A clear dependence of the thermomechanical fatigue response of these solder joints on Sn grain orientation was observed (Sn has a body centered tetragonal crystal structure). Fabricated joints tend to have three orientations in a cyclic twin relationship, but among the population of solder balls, this orientation triplet appears to be randomly oriented. In thermally cycled joints, solder balls with dominant Sn grains having the particular orientation with the c-axis nearly parallel to the plane of the substrate were observed to fail before neighboring balls with different orientations. This results from the fact that the coefficient of thermal expansion of Sn in the basal plane (along the alpha-axis) is half the value along the c-axis; joints observed to be damaged had the maximum coefficient of thermal expansion mismatch between solder and substrate at the joint interface, as well as a tensile stress modes during the hot part of the thermal cycle. Localized recrystallization was observed in regions of maximum strain caused by differential expansion conditions, and its connection with crack nucleation is discussed. View full abstract»

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  • 48. PCM thermal control unit for portable electronic devices: experimental and numerical studies

    Page(s): 116 - 125
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    This paper investigates the effectiveness of a thermal control unit (TCU) for portable electronic devices by performing experimental and numerical analyses. The TCU objective is to improve thermal management of electronic devices when their operating time is limited to a few hours. It is composed of an organic phase change material (PCM) and a thermal conductivity enhancer (TCE). To overcome the relatively low thermal conductivity of the PCM, a TCE is incorporated into the PCM to boost its conductivity. The TCU structure is complex, and modeling an electronic device with it requires time and effort. Hence, this research develops approximate, yet effective, solutions for modeling the TCU, which employ effective thermo-physical properties. The TCU component properties are averaged and a single TCU material is considered. This approach is evaluated by comparing the numerical predictions with the experimental results. The numerical model is then used to study the effect of important parameters that are experimentally expensive to examine, such as the PCM latent heat, Stefan number, and heat source power. It is shown that the TCU can provide a reliable solution to portable electronic devices, which avoids overheating and thermally-induced fatigue, as well as a solution which satisfies the ergonomic requirement. View full abstract»

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  • 49. Interfacial Degradation Mechanism of Au/Al and Alloy/Al Bonds Under High Temperature Storage Test: Contamination, Epoxy Molding Compound, Wire and Bonding Strength

    Page(s): 731 - 744
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    In this paper, the effects of Al pad contamination, epoxy molding compound [biphenyl (BP) and ortho-cresol novolac (OCN)] and wire (Au and alloy) on the propensity for the interfacial degradation of wire bond in a quad flap package under high temperature storage (HTS) tests at 125degC, 150degC, and 170degC are meticulously investigated. The interfacial degradation intends to be explicated in regards to change in surface morphology of Au-Al and alloy-Al intermetallic compound (IMC) and bonding strength as a function of HTS test. The combination of atomic force microscope and Auger electron spectrometry reveals that initial bonding strengths from wire pull and ball shear test decrease with increasing the thickness of contamination layer on Al pad, carbon and oxygen, and subsequent surface roughness. Indeed, the plasma exposure on Al pad prior to wire bonding enhances both mechanical bonding strengths up to 10% and 15%. It is found that the failure behaviors at 125degC are dissimilar to 150degC and 170degC. We first report that Sb diffused from the OCN exists at the intermetallics of Au-Al bonds, leading to rapidly deteriorate mechanical integrity. Furthermore, inductively coupled plasma mass spectrometry affirms that the OCN is a resource of Br. Above 150degC, the interdiffusion of Br and Sb from the OCN significantly impacts the integrity of Au-Al bonds. In turn, such physical degradation mechanism governed by Sb and Br can be linearly accelerated. It is also found that in the case of Au-Al bonds, the life time with the BP is much longer than that with the OCN under the given HTS tests due to less content of halogen ions. In contrast, neither Sb nor Br was found from the intermetallic layers of alloy-Al bond encapsulated with the OCN and BP. Thus, alloy-Al bonding strengths are intact even after longer stressing. With an alloy wire having Pd as an impurity, the growth kinetics of IMC fueled by Br and Sb seems to be sluggish, providing better reliability than Au wire.- - Obviously, lower flame retardants and higher are critical intrinsic material properties that should be taken into account when a new epoxy molding compound is introduced to pursue cost effectiveness without loosing reliability. Finally, upon painstaking work over a wide range of analyses herein, a quality affordable guideline for the selection of wire type associated with epoxy molding compound that can ensure the long-term reliability is presented in order to secure reliable supplyline management as well as package assembler. View full abstract»

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  • 50. Thermal design and optimization of natural convection polymer pin fin heat sinks

    Page(s): 238 - 246
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    The design and optimization methodology of a thermally conductive polyphenylene sulphide (PPS) polymer staggered pin fin heat sink, for an advanced natural convection cooled microprocessor application, are described using existing analytical equations. The geometric dependence of heat dissipation and the relationships between the pin fin height, pin diameter, horizontal spacing, and pin fin density for a fixed base area and excess temperature are discussed. Experimental results of a pin finned thermally conductive PPS heat sink in natural convection indicate substantially high thermal performance. Numerical results substantiate analytical modeling results for heat sinks within the Aihara et al. fin density range. The cooling rates and coefficient of thermal performance, COPT, that relates cooling capability to the energy invested in the formation of the heat sink, has been determined for such heat sinks and compared with conventional aluminum heat sinks. View full abstract»

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IEEE Transactions on Components and Packaging Technologies publishes research and applications articles on the modeling, building blocks, technical infrastructure, and analysis underpinning electronic, photonic, MEMS and sensor packaging.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

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Editor-in-Chief
Koneru Ramakrishna
Freescale Semiconductor, Inc.