# IEEE Electron Device Letters

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• ### GaN Nanowire n-MOSFET With 5 nm Channel Length for Applications in Digital Electronics

Publication Year: 2017, Page(s):859 - 862
| | PDF (729 KB) | HTML

We study the performance of GaN nanowire n-MOSFETs (GaN-NW-nFETs) with a channel length, Lg = 5 nm based on fully ballistic quantum transport simulations. Our simulation results show high ION = 1137μA/μm and excellent on-off characteristics with Q = gm/SS = 188 μS-decade/μm-mV calculated for Ioff = 1 nA/μm and VGS = VDS... View full abstract»

• ### 200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration

Publication Year: 2017, Page(s):918 - 921
| | PDF (1176 KB) | HTML

Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-perfor... View full abstract»

• ### Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Publication Year: 2017, Page(s):1657 - 1660
| | PDF (1131 KB) | HTML

This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell... View full abstract»

• ### High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates

Publication Year: 2017, Page(s):509 - 512
| | PDF (917 KB) | HTML

This letter reports a GaN vertical fin power field-effect-transistor structure with submicron fin-shaped channels on bulk GaN substrates. In this vertical transistor design only n-GaN layers are needed, while no material regrowth or p-GaN layer is required. A combined dry/wet etch was used to get smooth fin vertical sidewalls. The fabricated transistor demonstrated a threshold voltage of 1 V and s... View full abstract»

• ### Breakdown Enhancement and Current Collapse Suppression by High-Resistivity GaN Cap Layer in Normally-Off AlGaN/GaN HEMTs

Publication Year: 2017, Page(s):1567 - 1570
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In this letter, a device structure of high-resistivity-cap-layer HEMT (HRCL-HEMT) is developed for normally-off p-GaN gate HEMT toward high breakdown voltage and low current collapse. It demonstrates that the breakdown capability and current collapse of the device were effectively improved due to the introduction of a thick HR-GaN cap layer. The fabricated HRCL-HEMT exhibits a high breakdown volta... View full abstract»

• ### Analysis of the Gate Capacitance–Voltage Characteristics in p-GaN/AlGaN/GaN Heterostructures

Publication Year: 2017, Page(s):1696 - 1699
| | PDF (915 KB) | HTML

In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the ${C}$ – ${V}$ behavior depends on the different processing conditions... View full abstract»

• ### Improved Hysteresis and Reliability of MoS2 Transistors With High-Quality CVD Growth and Al2O3 Encapsulation

Publication Year: 2017, Page(s):1763 - 1766
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We report considerable improvement in the hysteresis and reliability of MoS2 field-effect transistors (FETs) achieved by chemical vapor deposition (CVD) of single-layer MoS2 and dielectric encapsulation. Our results show that a high-quality 15-nm thick Al2O3 layer allows for an efficient protection of the devices from adsorbent-type trapping sites. Combi... View full abstract»

• ### Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Publication Year: 2017, Page(s):44 - 47
| | PDF (686 KB) | HTML

The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated high-k-metal-gate logic dev... View full abstract»

• ### Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery

Publication Year: 2017, Page(s):1379 - 1382
| | PDF (1409 KB) | HTML

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 10<... View full abstract»

• ### Low-subthreshold-swing tunnel transistors

Publication Year: 2006, Page(s):297 - 300
Cited by:  Papers (259)  |  Patents (3)
| | PDF (176 KB) | HTML

A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests p... View full abstract»

• ### Proposal of a Single Nano-Magnet Memory Device

Publication Year: 2017, Page(s):1665 - 1668
| | PDF (622 KB) | HTML

We propose a non-volatile memory device using ferromagnetic (FM) contacts fabricated on a channel exhibiting spin-momentum locking observed in diverse materials with spin-orbit coupling like heavy metals and topological insulators. The writing is enabled by the current induced spin–orbit torque, which has been used previously to switch the storage layer of a magnetic tunnel junction (MTJ). ... View full abstract»

• ### 900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain

Publication Year: 2017, Page(s):1704 - 1707
| | PDF (1682 KB) | HTML

In this letter, we present high-performance GaN-on-Si metal-oxide-semiconductor high electron mobility transistors with record reverse-blocking (RB) capability. By replacing the conventional ohmic drain with a hybrid tri-anode Schottky drain, a high reverse breakdown voltage ( ${V}_{text {B}}^{text {R}}$ ) of −900 V was ... View full abstract»

• ### Effect of Drift Layer on the Breakdown Voltage of Fully-Vertical GaN-on-Si p-n Diodes

Publication Year: 2017, Page(s):1720 - 1723
| | PDF (1954 KB) | HTML

This letter reports on the epitaxial growth and device fabrication of metal-organic chemical vapor deposition grown fully vertical GaN-on-Si p-n diodes. A strong dependence in the electrical characteristics and epitaxial growth of n−-GaN drift layer was revealed by analyzing the threading dislocations, and carrier properties of the drift layers and current-voltage characteristics... View full abstract»

• ### Implementing p-bits With Embedded MTJ

Publication Year: 2017, Page(s):1767 - 1770
| | PDF (974 KB) | HTML

Magnetic tunnel junctions (MTJs) utilizing unstable magnets with low barriers have been shown to be well-suited for the implementation of random number generators (RNGs). It has recently been shown that completely new applications involving optimization, inference, and invertible Boolean logic would be enabled if many RNGs can be interconnected to form large scale correlated networks. However, thi... View full abstract»

• ### Impact of Trench Dimensions on the Device Performance of GaN Vertical Trench MOSFETs

Publication Year: 2017, Page(s):1559 - 1562
| | PDF (619 KB) | HTML

In this letter, we have examined the impact of trench dimensions on the breakdown voltage and ON-resistance of trench MOSFETs fabricated on sapphire and bulk GaN substrates. Contrary to simulation studies, the breakdown voltage decreased with an increase in trench dimensions in devices fabricated on sapphire substrates. However, such breakdown voltage dependence with trench dimensions was not obse... View full abstract»

• ### Enhanced gm and fT With High Johnson’s Figure-of-Merit in Thin Barrier AlGaN/GaN HEMTs by TiN-Based Source Contact Ledge

Publication Year: 2017, Page(s):1563 - 1566
| | PDF (907 KB) | HTML

A high combination of transconductance(gm), current gain cutoff frequency (fT) and three terminal breakdown voltage was achieved using thin barrier AlGaN/GaN HEMTs and TiN-based source contact ledge. The sheet resistance is effectively reduced, whereas the peak extrinsic trans-conductance is improved by 24% from 334 to 415 mS/mm. The thin barrier AlGaN/GaN HEMTs with TiN-base... View full abstract»

• ### First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET

Publication Year: 2017, Page(s):1575 - 1578
| | PDF (750 KB) | HTML

Gate dielectricplays an integral role in advancing the performance and reliability of GaN-based transistors. Si-alloying of aluminum oxide (Al2O3) dielectrics have been shown to provide a promising route to improve gate dielectric properties in GaN. In this letter, we report on the first demonstration of a GaN FET with aluminum silicon oxide (AlSiO) as the gate dielectric. Ve... View full abstract»

• ### Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined With Thermal Analysis

Publication Year: 2017, Page(s):1653 - 1656
| | PDF (1000 KB) | HTML

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements.. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the ... View full abstract»

• ### Low-Frequency Noise in III–V Nanowire TFETs and MOSFETs

Publication Year: 2017, Page(s):1520 - 1523
| | PDF (557 KB) | HTML

We present a detailed analysis of low-frequency noise (LFN) measurements in vertical III-V nanowire tunnel field-effect transistors (TFETs), which help to understand the limiting factors of TFET operation. A comparison with LFN in vertical metal-oxide semiconductor field-effect transistors with the same channel material and gate oxide shows that the LFN in these TFETs is dominated by the gate oxid... View full abstract»

• ### A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Publication Year: 2017, Page(s):1547 - 1550
| | PDF (783 KB) | HTML

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier in 40-nm CMOS. Using a simple, CMOS-compatible technique, the pixel is capable of passive quenching and active recharge at voltages well above th... View full abstract»

• ### Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

Publication Year: 2016, Page(s):245 - 248
Cited by:  Papers (15)
| | PDF (1575 KB) | HTML

We demonstrate a nearly hysteresis-free sub60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal-oxide-semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS <;60 mV/decade is observed over three orders of magnitude (i.e., 10 pA/μm~10 nA/μm of drain current) and at large drain current levels. However, the extent of hysteresi... View full abstract»

• ### A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

Publication Year: 2017, Page(s): 1
| | PDF (503 KB)

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon (MFIS) capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-anneal is n... View full abstract»

• ### High-performance heat sinking for VLSI

Publication Year: 1981, Page(s):126 - 129
Cited by:  Papers (1492)  |  Patents (180)
| | PDF (440 KB)

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. ... View full abstract»

• ### Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications

Publication Year: 2017, Page(s):1220 - 1223
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We perform a comparative study of HfO2 and Ta2O5 resistive switching memory (RRAM) devices for their possible application as electronic synapses. By means of electrical characterization and simulations, we link their electrical behavior (digital or analog switching) to the properties and evolution of the conductive filament (CF). More specifically, we identify that... View full abstract»

• ### Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Publication Year: 2016, Page(s):111 - 114
Cited by:  Papers (19)
| | PDF (791 KB) | HTML

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg = 100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We sh... View full abstract»

• ### Slanted Tri-Gates for High-Voltage GaN Power Devices

Publication Year: 2017, Page(s):1305 - 1308
| | PDF (1037 KB) | HTML

In this letter, we introduce and demonstrate the concept of slanted tri-gates to enhance the breakdown voltage (VBR) in lateral GaN power devices. Conventionally, field plates (FPs) are used to enhance the VBR by distributing more homogeneously the electric field near the gate electrode, which is mainly determined by their pinch-off voltage (Vp). These FPs however rely on a v... View full abstract»

• ### Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO2–Based High-k Dielectrics

Publication Year: 2017, Page(s):1524 - 1527
| | PDF (710 KB) | HTML

In order to produce a dynamic random access memory (DRAM) of 20 nm or less, the most important concern regarding development is to reduce the leakage current degradation of the capacitor using high-k dielectrics. We studied the effect of defect sources present after the formation of the capacitor and measured the leakage current characteristics of the capacitor using the dielectric breakdown degra... View full abstract»

• ### Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits

Publication Year: 2017, Page(s): 1
| | PDF (3096 KB)

We report on the impact of process variations on short-channel negative capacitance (NC) based FinFETs through statistical Monte Carlo simulations using a physics based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NCFinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectr... View full abstract»

• ### Ge-Doped ${\beta }$ -Ga2O3 MOSFETs

Publication Year: 2017, Page(s):775 - 778
| | PDF (991 KB) | HTML

We report on MOSFETs fabricated on Ge-doped β-Ga2O3 homoepitaxial material grown by molecular beam epitaxy on (010) Fe-doped semi-insulating substrates. The Ge-doped channel devices performed similar to previously reported devices with Sn- and Si-doped channels with the drain current ON/OFF ratios of >108 and the saturated drain current of >... View full abstract»

• ### A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory

Publication Year: 2017, Page(s):1669 - 1672
| | PDF (743 KB) | HTML

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Mean... View full abstract»

• ### Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Publication Year: 2017, Page(s):1555 - 1558
| | PDF (992 KB) | HTML

A novel superjunction (SJ) lateral double-diffused MOSFET ( >950 V) with a thin layer SOI combining the advantage of low specific on-resistance Ron,sp of the SJ and the high breakdown voltage VB of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably... View full abstract»

• ### GaN DHFETs Having 48% Power Added Efficiency and 57% Drain Efficiency at $V$ -Band

Publication Year: 2017, Page(s):1708 - 1711
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We report the state-of-the-art $V$ -band power performance of a scaled 40-nm gate length Al0.23Ga0.77N/AlN/GaN/Al0.08Ga0.92N double heterojunction field effect transistor (DHFET). The $200~mu text{m}$ ( View full abstract»

• ### Power semiconductor device figure of merit for high-frequency applications

Publication Year: 1989, Page(s):455 - 457
Cited by:  Papers (291)  |  Patents (5)
| | PDF (290 KB)

A figure of merit (the Baliga high-frequency figure of merit) is derived for power semiconductor devices operating in high-frequency circuits. Using this figure of merit, it is predicted that the power losses incurred in the power device will increase as the square root of the operating frequency and approximately in proportion to the output power. By relating the device power dissipation to the i... View full abstract»

• ### Enhancement-Mode AlGaN/GaN Nanowire Channel High Electron Mobility Transistor With Fluorine Plasma Treatment by ICP

Publication Year: 2017, Page(s):1421 - 1424
| | PDF (1248 KB) | HTML

This letter reports on a novel enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) that combines nanowire channel and fluorine plasma treatment using inductively coupled plasma (ICP). Compared with the conventional HEMTs, the threshold voltage of E-mode HEMT shifts from -2.8 to +0.7 V, and the Schottky reverse leakage current is reduced by one order of magnitude. The devic... View full abstract»

• ### Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Publication Year: 2017, Page(s):1485 - 1488
| | PDF (679 KB) | HTML

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs... View full abstract»

• ### InAlN/GaN HEMTs on Si with high fT of 250 GHz

Publication Year: 2017, Page(s): 1
| | PDF (863 KB)

In this work InAlN/GaN high electron mobility transistors (HEMTs) with 40-200 nm rectangular gates and 300-700 nm source-to-drain distances were fabricated on Si substrates. The device with 40 nm gate and 300 nm source-to-drain distance exhibited a high drain current of 2.66 A/mm, a transconductance (gm) of 438 mS/mm and a high current gain cut-off frequency (fT) of 250 GHz. To the best of our kno... View full abstract»

• ### Oxide-Based Electric-Double-Layer Thin-Film Transistors on a Flexible Substrate

Publication Year: 2017, Page(s):1680 - 1683
| | PDF (764 KB) | HTML

Flexible electric-double-layer (EDL) InGaZnO thin-film transistors (TFTs) were fabricated on a plastic substrate at room temperature. A large EDL gate capacitance, 0.22 $mu text{F}$ /cm2, at 20 Hz was achieved using 200-nm-thick radio frequency magnetron sputtered porous SiO2 as the dielectric layer, whic... View full abstract»

• ### A Novel High Holding Voltage Dual-Direction SCR With Embedded Structure for HV ESD Protection

Publication Year: 2017, Page(s):1716 - 1719
| | PDF (920 KB) | HTML

In order to boost the holding voltage of the multi-fingered dual-direction silicon-controlled rectifier, a novel embedded topology is proposed instead of the traditional interdigital multi-finger arrangement. It is verified in a 0.5- $mu text{m}$ 18-V standard CDMOS process and applied to the high-voltage electro-static discha... View full abstract»

• ### Field Plate Design for Low Leakage Current in Lateral GaN Power Schottky Diodes: Role of the Pinch-off Voltage

Publication Year: 2017, Page(s):1298 - 1301
| | PDF (1701 KB) | HTML

In this letter, we demonstrate a general model to reduce the reverse leakage current (IR) in high-voltage AlGaN/GaN Schottky diodes (SBDs) by engineering the pinchoff voltage (Vp) of their field plates (FPs). The maximum voltage drop at the Schottky junction (VSCH) in the OFF state can be significantly-decreased by reducing |Vp|, which leads to a drastic... View full abstract»

• ### Ferroelectric Oscillators and Their Coupled Networks

Publication Year: 2017, Page(s):1614 - 1617
| | PDF (1367 KB) | HTML

We propose ferroelectric field-effect transistor (FEFET)-based realization of non-linear, relaxation oscillators and their coupled networks. To control oscillations, we utilize a unique physics of FEFETs: the dynamic voltage controllabilityof the location and the width of the hysteresis loop. Such ferroelectric-basedcomplex, dynamical systems can lead to efficient physical platforms for alternativ... View full abstract»

• ### Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor

Publication Year: 2017, Page(s):1661 - 1664
| | PDF (1359 KB) | HTML

We present a simple model to evaluate the sharpness of the band edges for tunnel field-effect transistors (TFETs) by comparing the subthreshold swing and the conductance in the negative differential resistance region. This model is evaluated using experimental data from InAs/InGaAsSb/GaSb nanowire TFETs with the ability to reach a subthreshold swing well below the thermal limit. A device with the ... View full abstract»

• ### Intrinsic speed limit of negative capacitance transistors

Publication Year: 2017, Page(s):1328 - 1330
| | PDF (568 KB) | HTML

The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the... View full abstract»

• ### Self-Limited CBRAM With Threshold Selector for 1S1R Crossbar Array Applications

Publication Year: 2017, Page(s):1532 - 1535
| | PDF (785 KB) | HTML

In this letter, we demonstrate a self-limited conductive-bridging random access memory (CBRAM) that removes the necessity for external current compliance in a one selector-one resistor (1S1R) architecture. The standard Ge2Sb2Te5 (GST) is used as a CBRAM switching layer. In addition, Te-rich GST is also considered. Their performance is then compared. Both samples ex... View full abstract»

• ### High Voltage Gain Inverters From Artificially Stacked Bilayer CVD Graphene FETs

Publication Year: 2017, Page(s):1747 - 1750
| | PDF (1176 KB) | HTML

In this letter, we report on inverters made from graphene field effect transistors with channels of artificially stacked bilayer graphene (ASBLG). The materials were grown by scalable chemical vapor deposition. The devices demonstrate enhanced voltage gain ( $mathrm{A}_mathrm {v}$ ) figures at relatively lower input voltages wh... View full abstract»

• ### Vertical GaN Junction Barrier Schottky Rectifiers by Selective Ion Implantation

Publication Year: 2017, Page(s):1097 - 1100
| | PDF (915 KB) | HTML

This letter demonstrates vertical GaN junction barrier Schottky (JBS) rectifiers fabricated with novel ion implantation techniques. We used two different methods to form the lateral p-n grids below the Schottky contact: 1) Mg implantation into n-GaN to form p-wells and 2) Si implantation into p-GaN to form n-wells. Specific differential ON-resistances (RON) of 1.5-2.5 mΩ · cm2 View full abstract»

• ### In-Plane-Gate GaN Transistors for High-Power RF Applications

Publication Year: 2017, Page(s):1413 - 1416
| | PDF (798 KB) | HTML

In-plane-gatefield-effecttransistors(IPGFETs) offer an innovative device architecture in which the channel conductivity is modulated by the electric field from the 2D electron gas in the two adjacent in-plane gates, isolated by etched trenches. The planar nature of the gate electrode yields a huge reduction in parasitic gate capacitance, which can lead to much higher frequency. Moreover,the fabric... View full abstract»

• ### High-Performance Depletion/Enhancement-ode $\beta$ -Ga2O3 on Insulator (GOOI) Field-Effect Transistors With Record Drain Currents of 600/450 mA/mm

Publication Year: 2017, Page(s):103 - 106
Cited by:  Papers (3)
| | PDF (760 KB) | HTML

In this letter, we report on high-performance depletion/enhancement-mode β-Ga2O3 on insulator (GOOI) field-effect transistors (FETs) with record high drain currents (ID) of 600/450 mA/mm, which are nearly one order of magnitude higher than any other reported ID values. The threshold voltage (VT) can be modulated by varying the thickness... View full abstract»

• ### Self-Aligned AlGaN/GaN FinFETs

Publication Year: 2017, Page(s):1445 - 1448
| | PDF (940 KB) | HTML

We have demonstrated highly scaled, self-aligned AlGaN/GaN fin-shaped field-effect transistors (FinFETs), which were fabricated using e-beam lithography and a regrown n+ GaN ohmic process with a sacrificial dummy gate. Our devices were very aggressively scaled, with fin widths, gate length, and source drain spacing as small as 50,60, and 200 nm, respectively.DC characteristics, when normalized to ... View full abstract»

• ### A Graphene Field-Effect Device

Publication Year: 2007, Page(s):282 - 284
Cited by:  Papers (567)  |  Patents (29)
| | PDF (226 KB) | HTML

In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-... View full abstract»

• ### Natural Local Self-Boosting Effect in 3D NAND Flash Memory

Publication Year: 2017, Page(s):1236 - 1239
| | PDF (843 KB) | HTML

This letter examined the natural local self-boosting effect of an inhibited channel in three-dimensional (3D) NAND flash memory. The inhibited channel in the 3D NAND flash structure can be in the floating state easily, because its channel is not connected directly to its substrate. Despite the application of the global self-boosted program-inhibit scheme, the selected wordline cell is localized au... View full abstract»

## Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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## Meet Our Editors

Editor-in-Chief

Tsu-Jae King Liu
tking@eecs.berkeley.edu