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IEE Proceedings E - Computers and Digital Techniques

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  • 1. Four-slot fully asynchronous communication mechanism

    Publication Year: 1990, Page(s):17 - 30
    Cited by:  Papers (17)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1328 KB)

    The paper is concerned with communication mechanisms in which a record in shared memory is maintained by a writer to provide a coherent and up-to-date data reference which may be accessed at any time by a reader. The dynamic properties of several possible designs are briefly discussed before concentrating on a fully asynchronous form called a four-slot mechanism. This takes its name from the four-... View full abstract»

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  • 2. Parallel VLSI algorithm for stable inversion of dense matrices

    Publication Year: 1989, Page(s):575 - 580
    Cited by:  Papers (25)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (472 KB)

    A fast, efficient, parallel algorithm for stable matrix inversion based on Givens plane rotations is described. The algorithm is implemented on VLSI systolic architecture that is capable of inverting any n*n nonsingular dense matrix in 5n units of time, including I/O time. The array architecture consists of n2+n processing elements (PEs) arranged as a cascade of two triangular arrays of... View full abstract»

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  • 3. VLSI design of inverse-free Berlekamp-Massey algorithm

    Publication Year: 1991, Page(s):295 - 298
    Cited by:  Papers (54)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (188 KB)

    The Berlekamp-Massey iterative algorithm for decoding BCH codes is modified to eliminate the calculation of inverses. This new algorithm is useful in the practical application of multiple-error-correcting BCH or RS codes. A VLSI architecture is developed for this algorithm. View full abstract»

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  • 4. Silicon-on-insulator technology

    Publication Year: 1986, Page(s):106 - 116
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1913 KB)

    The last few years have seen considerable progress in the development of techniques for producing silicon-on-insulator (SOI) substrates suitable for fabrication of high performance devices/circuits. Among the most promising of the new ideas are those based on buried dielectric formation by ion implantation (oxygen or nitrogen), recrystallisation of deposited polycrystalline silicon-on-insulator (u... View full abstract»

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  • 5. Remote password authentication with smart cards

    Publication Year: 1991, Page(s):165 - 168
    Cited by:  Papers (44)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (236 KB)

    A remote password authentication scheme based on the Chinese remainder theorem is proposed. The scheme can verify the remote password without verification tables. In the initial phase, the password generation centre generates and assigns a password corresponding to each user. The ideas of smart cards and the identity-based signature scheme introduced by Shamir (1984) are employed in this phase. Ea... View full abstract»

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  • 6. The Megacell concept: an approach to painless custom design

    Publication Year: 1985, Page(s):91 - 98
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1650 KB)

    Megacell is a complete design package for the creation of complex VLSI chips. It allows system engineers to develop their own custom integrated circuits. The challenge of Megacell was to create a design system that would exploit fully the low-power and high-speed performance of a UK developed 2 ¿¿m CMOS technology, while producing the silicon utilisation efficiency typical of full custom design. T... View full abstract»

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  • 7. Object-background segmentation using new definitions of entropy

    Publication Year: 1989, Page(s):284 - 295
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (980 KB)

    The definition of Shannon's entropy in the context of information theory is critically examined and some of its applications to image processing problems are reviewed. A new definition of classical entropy based on the exponential behaviour of information-gain is proposed along with its justification. Its properties also include those of Shannon's entropy. The concept is then extended to fuzzy set... View full abstract»

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  • 8. Implementation issues of sigmoid function and its derivative for VLSI digital neural networks

    Publication Year: 1992, Page(s):207 - 214
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    Proposes a number of different implementations for the first derivative of the sigmoid function. The implementation of the sigmoid function employs a powers-of-two piecewise linear approximation. The best implementation scheme for the derivative is suggested based on overall speed performance (circuit speed and training time) and hardware requirements. View full abstract»

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  • 9. Symmetric degree-four chordal ring networks

    Publication Year: 1990, Page(s):310 - 318
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (696 KB)

    Techniques for analysing symmetric chordal ring networks of degree four are presented and expressions for the network diameter and the mean internode distance are derived. The network incorporates the maximum number of nodes for a given diameter, and has a communications cost, measured either as network diameter or as the mean internode distance, of O( square root (N)). Possible modifications to t... View full abstract»

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  • 10. Simplified procedure for correcting both errors and erasures of Reed-Solomon code using Euclidean algorithm

    Publication Year: 1988, Page(s):318 - 324
    Cited by:  Papers (15)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (440 KB)

    It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial and the error evaluator polynomial in Berlekamp's key equation that is needed to decode a Reed-Solomon (RS) code. In the paper, a simplified procedure is developed and proved to correct erasures as well as errors by replacing the initial condition of the Euclidean ... View full abstract»

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  • 11. Buffer analysis for asynchronous data interpolation in analogue speech

    Publication Year: 1981, Page(s):229 - 238
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (874 KB)

    The store-and-forward buffer required for asynchronous data interpolation (ADI) in analogue speech is analysed using a queueing model with single server having 1st-order Markov interruptions. The buffer-content probability generating function and probability mass function are derived. It is shown that the empty-buffer probability in the finite buffer equals that of the infinite buffer with its off... View full abstract»

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  • 12. Image registration using an image graph and its application to map matching

    Publication Year: 1991, Page(s):79 - 84
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (440 KB)

    A representation of line images by an algebraic expression is proposed and image registration between two maps by use of matching of the line segments is discussed using this expression. In this method, input map images are transformed into line images in which line segments are expressed by piecewise linear lines using unit vectors. Next, the structure of the line images is represented by image g... View full abstract»

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  • 13. Partitioning concurrent VLSI simulation programs onto a multiprocessor by simulated annealing

    Publication Year: 1987, Page(s):24 - 30
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (859 KB)

    Efficiently loading concurrent programs onto multiprocessor architectures is a graph partitioning problem where both the edges and vertices are weighted. The corresponding optimisation problem is computationally NP-hard, and the optimal solution can only be found by exhaustively examining all possible partitioning configurations. Near-optimal solutions can be found by using heuristic algorithms su... View full abstract»

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  • 14. SWIFT: stack-based microprocessor for LISP and PROLOG

    Publication Year: 1991, Page(s):299 - 304
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    SWIFT is a stack-based microprocessor designed for the efficient execution of LISP and PROLOG. The paper describes the architecture of a VLSI implementation of SWIFT which gives more than 1 Mlips performance, yet only requires 16K gates. The processor was designed at a high level in ELLA and was synthesised to the gate level using LOCAM. View full abstract»

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  • 15. Sequences of linear-feedback shift registers with nonlinear-feedforward logic

    Publication Year: 1983, Page(s):174 - 176
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (393 KB)

    Analysis of sequences generated by a linear feedback shift register with nonlinear feedforward logic is performed. Emphasis is focused on the period, the complexity, the number of ones and zeros, as well as the autocorrelation function of the resulting output sequences. View full abstract»

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  • 16. Message-efficient distributed mutual exclusion incorporating the 'least recently used' fairness criterion

    Publication Year: 1992, Page(s):501 - 504
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (320 KB)

    The fairness criterion is a crucial attribute of distributed mutual exclusion algorithms. This criterion determines for how long a node, which has issued a request for executing a critical section, has to wait. All solutions to the distributed mutual exclusion problem are expected to be starvation free. Ensuring starvation freedom alone may not be sufficient in large distributed systems with onlin... View full abstract»

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  • 17. Algorithms for software implementations of RSA

    Publication Year: 1989, Page(s):166 - 170
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (328 KB)

    Two new algorithms that facilitate the implementation of RSA in software are described. Both algorithms are essentially concerned with performing modular arithmetic operations on very large numbers, which could be of potential use to applications other than RSA. One algorithm performs modular reduction and the other performs modular multiplication. Both algorithms are based on the use of look-up t... View full abstract»

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  • 18. Design of synchronisers: a review

    Publication Year: 1989, Page(s):557 - 564
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (700 KB)

    The synchronisation of asynchronous inputs and metastability in synchronisers have haunted designers of digital systems for a long time. Even though the metastable behaviour of latches and other similar devices is now well understood, it is still a major limitation in digital systems which involve frequent asynchronous interaction. The problem has been studied both theoretically and practically an... View full abstract»

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  • 19. Industrial applications of computer vision since 1982

    Publication Year: 1988, Page(s):117 - 136
    Cited by:  Papers (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2364 KB)

    During the past six years, the use of computer vision systems for industrial applications has become increasingly widespread. In the paper, the application of vision in this context is surveyed and reviewed, according to the principal current application areas of automated visual inspection and visually guided robotic manipulation. Additionally, recently published research and development work for... View full abstract»

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  • 20. Use of multiplexers in direct synthesis of ASM-based designs

    Publication Year: 1986, Page(s):194 - 200
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (882 KB)

    Techniques are described for translating an ASM chart or table directly into a variety of synthesis forms. These include PROM-, FPLA- and multiplexer-based implementations. A method for improving the circuit economy based on the preselection of qualifiers by means of multiplexers is presented. An algorithm for the simplification of multiplexer networks is also included. View full abstract»

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  • 21. Design of a high-performance IIR digital filter chip

    Publication Year: 1992, Page(s):195 - 202
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (592 KB)

    The design of a novel high-performance IIR digital filter chip is presented. The chip has been implemented using 1.5 mu m double-layer metal CMOS technology. The filter chip operates on an 11-bit two's-complement input data, a 12-bit two's-complement coefficient word and produces a two's-complement 14-bit output. The main component of the chip is a fine grained systolic array architecture that int... View full abstract»

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  • 22. Bus scheduling for a multiple-processor system with shared buses

    Publication Year: 1987, Page(s):288 - 294
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (681 KB)

    The operation and performance of a multiple-processor system with shared buses is analysed. The model developed is applicable to real-time computations consisting of two pipelined tasks in which the first task is partitioned into a number of independent subtasks on separate processors. These processors transmit their output data to the processor(s) executing the second task over shared buses. When... View full abstract»

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  • 23. A queueing analysis of a symmetric multiprocessor with shared memories and buses

    Publication Year: 1983, Page(s):83 - 89
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (899 KB)

    The performance of a symmetric multiprocessor system on the level of memory requests is studied. The multiprocessor consists of a number of identical processors, each having its local private memory and each being connected via a system of identical buses to all global memory modules. The system is modelled by a Markovian queueing network and solved approximately by a hierarchical decomposition te... View full abstract»

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  • 24. Design and verification of regular synchronous circuits

    Publication Year: 1986, Page(s):295 - 304
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1259 KB)

    A VLSI design language, µFP, is presented and it is shown how it can be used in the development of regular array circuits. The higher order functions which are used to build circuit descriptions have geometric as well as semantic interpretations. They allow common circuit forms to be described simply and concisely. The language obeys various algebraic laws, and circuits are developed by transform... View full abstract»

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  • 25. Study of the behaviour of Hubnet

    Publication Year: 1993, Page(s):134 - 144
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (704 KB)

    The behaviour of Hubnet is studied and analysed. A simulation model is developed from which the effect of the retry time on the performance of Hubnet is studied. It is shown that there is an inherent dependency between the packet length and the retry time. According to this dependency, retry time-values which are factors of the packet length exhibit superior performance in terms of reduced average... View full abstract»

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  • 26. SST: scan self-test for sequential machines

    Publication Year: 1989, Page(s):569 - 574
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    A new scan, built-in self-test technique called SST for testing sequential machines (finite state machines) is presented. This technique uses an external linear feedback shift register (LFSR) or a cellular-automaton-based (CA-based) test pattern generator to generate exhaustive test patterns. These patterns are scanned into the machine and the output responses are scanned out for comparison. It is... View full abstract»

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  • 27. Flexible systolic architecture for VLSI FIR filters

    Publication Year: 1992, Page(s):170 - 172
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (184 KB)

    A new systolic array architecture with a spiral structure of interconnections is proposed for very-high-throughput VLSI FIR filters. This architecture consists of L*K cells, where K is the filter order and 1 View full abstract»

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  • 28. Orbital architectures with dynamic reconfiguration

    Publication Year: 1987, Page(s):281 - 287
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (745 KB)

    Several broad classes of nonplanar arrays/architectures are analysed. Included in this are architectures which have a natural interpretation in terms of data flow on the surface of a torus, sphere, cylinder and other geometric forms. A definitive quantification is given of the several architectural classes and architectural reconfiguration is demonstrated to facilitate iterative computations. View full abstract»

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  • 29. Pruned-trellis search technique for high-rate convolutional codes

    Publication Year: 1989, Page(s):405 - 414
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (684 KB)

    A new method to search for high-rate convolutional codes is achieved by means of a pruned trellis. This makes possible a reduced search procedure that can not be accomplished by standard methods. This new search technique makes use of the concept of the expanded column distance function of a convolutional code. By use of this search procedure, codes are found with an optimum distance profile follo... View full abstract»

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  • 30. Hardware evaluation of mathematical functions

    Publication Year: 1981, Page(s):155 - 164
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1182 KB)

    The paper presents a family of algorithms for evaluating the elementary mathematical functions including division, sine, cosine, tangent, arctangent, logarithm, exponential and square root. The algorithms are based on continued products and continued sums, and generate the sum on a 2-bit-at-a-time basis. The only operations required are shifting, adding, subtracting and recall of prestored constan... View full abstract»

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  • 31. Optimal tile partition for space region of integrated circuits geometry

    Publication Year: 1993, Page(s):145 - 153
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (548 KB)

    An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas the authors OTP allows overlapping. This ... View full abstract»

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  • 32. Towards effective nonlinear cryptosystem design

    Publication Year: 1988, Page(s):325 - 335
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (756 KB)

    The paper describes the design of nonlinear Boolean functions. The first part reviews the case of Boolean functions of n variables. The second part addresses the problem of the generation of Boolean permutations to obtain the collection of nonlinear Boolean functions. View full abstract»

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  • 33. Microcomputer system specification using interval logic and a modified labelled-net model

    Publication Year: 1986, Page(s):223 - 234
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1370 KB)

    The application of interval logic and modified labelled-net models for system specification and verification is introduced. By means of interval logic and modified labelled-net models, system properties involving time interval information can be specified and verified. In interval logic, derivation rules are used to obtain the criteria on the time relationships for the correct implementation of th... View full abstract»

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  • 34. VLSI process compatible 8 bit CMOS DAC

    Publication Year: 1985
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (437 KB)

    The novel CMOS digital/analogue convertor is intended for use in cell-based semicustom designs. High speed and low power consumption have been achieved using a standard VLSI process without postprocess trimming. View full abstract»

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  • 35. Flag-algebra: a new concept for the realisation of fully parallel associative architectures

    Publication Year: 1989, Page(s):357 - 365
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (951 KB)

    The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented by a fla... View full abstract»

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  • 36. Deductive fault diagnosis in digital circuits: a survey

    Publication Year: 1989, Page(s):496 - 504
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (940 KB)

    Fault diagnosis in digital circuits is normally based on prior computation of fault symptoms using explicit fault models and simulation followed by matching of the observed symptoms of a faulty circuit with one of the sets of precomputed symptoms. Some attempts have been made, however, at diagnosis without fault simulation by deducing the location of a fault or faults from the observed symptoms an... View full abstract»

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  • 37. Time characteristics of IEEE 802.4 token bus protocol

    Publication Year: 1992, Page(s):81 - 87
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (516 KB)

    Timed token protocols have increased in importance with the growth of local area network (LAN) communications One of the most important timed token protocols is certainly IEEE 802.4, a standard given the name 'token bus', which represents one of the most interesting solutions to the problem of handling, on the same physical channel, the transmission of messages belonging to multiple priority class... View full abstract»

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  • 38. VLSI implementation of Tausworthe random number generator for parallel processing environment

    Publication Year: 1991, Page(s):138 - 146
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (712 KB)

    A fast Tausworthe-type random number generator has been implemented as a VLSI circuit on silicon for Monte-Carlo simulation purposes in a parallel multiprocessor system environment. The generator, which has uniform distribution, has been constructed for use as a peripheral device to be connected with each processor unit. General considerations for parallel random number generation are discussed an... View full abstract»

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  • 39. Improved fractal geometry based texture segmentation technique

    Publication Year: 1993, Page(s):233 - 241
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (772 KB)

    The problem of natural texture segmentation is considered. The technique is based on four texture features derived using the fractal geometry of images. These four features are fractal dimension (FD) of the original image, FD of above average (high) gray level image, FD of below (low) gray level image, and multifractal of order two. A modified box-counting approach is proposed to estimate the FD a... View full abstract»

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  • 40. Physical faults in MOS circuits and their coverage by different fault models

    Publication Year: 1988, Page(s):1 - 9
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits a... View full abstract»

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  • 41. Completely decentralised communication control in microcomputer clusters

    Publication Year: 1985, Page(s):333 - 338
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (710 KB)

    Very closely located single-board or single-chip microcomputers, co-operating for a common task, can be linked as clusters, with their sizes being changed arbitrarily depending on the task parallelism and the resources available from each node (microcomputer). Intracluster communications are handled by identical bus/memory arbiters, one in each node. The arbiters switch microprocessors and memorie... View full abstract»

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  • 42. Structural technique for fault-masking in asynchronous interfaces

    Publication Year: 1993, Page(s):81 - 91
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (892 KB)

    Asynchronous VLSI circuits have been proven to be more tolerant to persistent defects, such as stuck-at faults, than their clocked counterparts. However, such circuits are directly reactive to input stimuli and so they can be more vulnerable to transient faults at their inputs. The ability to tolerate such faults is most crucial for interface circuits, or transducers, which are the information ker... View full abstract»

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  • 43. Advanced automotive multiplexed wiring system

    Publication Year: 1986, Page(s):312 - 318
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (771 KB)

    The paper describes a wiring system which incorporates 4-bit microcontrollers to reduce costs. These devices may be custom produced with the specialised control program held on chip. Using these, a centralised control system with up to eight remote switching and monitoring units may be configured with a single data communications channel and power supply common to each. Standard automotive cable i... View full abstract»

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  • 44. Discrete logarithm hash function that is collision free and one way

    Publication Year: 1991, Page(s):407 - 410
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (284 KB)

    For suitable composite modulus n and suitable base a, the discrete logarithm hash function x to ax mod n is collision free and one way if factoring n is hard. Further results on the relation between the discrete logarithm problem and factoring are given. Some complexity theory issues are considered. View full abstract»

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  • 45. Heuristic model for task allocation in distributed computer systems

    Publication Year: 1991, Page(s):313 - 318
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (400 KB)

    In distributed computing systems, partitioning of application software into modules and proper allocation of modules among processors are important factors for efficient utilisation of resources. A method for static allocation of modules to processors, with the constraints of minimising interprocessor communication cost and load balancing is presented. The heuristic approach forms module clusters ... View full abstract»

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  • 46. TE design processes for successive-approximation A/D converter registers

    Publication Year: 1981, Page(s):79 - 83
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (543 KB)

    Transition equations (TEs) and the associated design processes provide an interesting, and often rewarding, approach to sequential-logic circuit design. However, these processes are ignored in most of the text books and many engineers are thus unaware of them. The paper sets out the salient features of the technique by taking the design of a successive-approximation register as an example. It is h... View full abstract»

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  • 47. VLSI and WSI associative string processors for structured data processing

    Publication Year: 1986, Page(s):153 - 162
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (918 KB)

    A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover,... View full abstract»

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  • 48. Universal architecture for matrix transposition

    Publication Year: 1992, Page(s):387 - 392
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (460 KB)

    A new real-time architecture for matrix transposition is presented. This architecture exploits the inherent parallelism and pipelining of the transposition operation resulting in an efficient mapping of the operation (algorithm) onto the structure. More importantly, this architecture is a universal implementation of executing matrix transposition because it allows data to flow in and out of the st... View full abstract»

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  • 49. Lifetime analyses of error-control coded semiconductor RAM systems

    Publication Year: 1982, Page(s):81 - 85
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (522 KB)

    The paper is concerned with developing quantitative results on the lifetime of coded random-access semiconductor memory systems. Although individual RAM chips are highly reliable, when large numbers of chips are combined to form a large memory system, the reliability may not be sufficiently high for the given application. In this case, error-correction coding is used to improve the reliability and... View full abstract»

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  • 50. Multiprocessor implementation of the logic function of a multiplexed wiring system for automotives

    Publication Year: 1982, Page(s):223 - 228
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (806 KB)

    The problems of conventional automotive wiring harnesses and how they can be minimised by multiplexing are discussed. The multiplexed wiring harness replaces the conventional harness with a cable bus carrying power and time-division multiplexed control signals to electronic modules that decode the control signals and activate power switches accordingly. An experimental multimicrocomputer multiplex... View full abstract»

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