# IEEE Embedded Systems Letters

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• ### Energy Efficient Outdoor Light Monitoring and Control Architecture Using Embedded System

Publication Year: 2016, Page(s):18 - 21
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In this letter, we propose an energy efficient ZigBee-based outdoor light monitoring and control system that can monitor and handle outdoor lights more efficiently as compared to the conventional systems. The proposed system uses the ZigBee-based wireless devices which allow more efficient lamps management. The designed system uses sensors to control and guarantee the optimal system parameters. To... View full abstract»

• ### Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing

Publication Year: 2017, Page(s):65 - 68
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Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in ... View full abstract»

• ### Testing Autonomous Vehicle Software in the Virtual Prototyping Environment

Publication Year: 2017, Page(s):5 - 8
Cited by:  Papers (1)
| | PDF (525 KB) | HTML

Modern vehicle is equipped with autonomous features, such as precollision system or adaptive cruise control to help people perform driving in a safer and more convenient way. The software complexity of those autonomous features is growing to accommodate various needs from users, which makes it more difficult to test their correctness. Virtual prototyping allows one to test the vehicle software in ... View full abstract»

• ### Virtualizing Programmable Logic Controllers: Toward a Convergent Approach

Publication Year: 2016, Page(s):69 - 72
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Modern programmable logic controllers (PLCs) are pervasive components in industrial control systems (ICSs) such as supervisory control and data acquisition, designed to control industrial processes autonomously or as part of a distributed system topology. Its success may be explained by its robustness and reliability, being one of the most enduring legacies on modern ICS, despite having evolved ve... View full abstract»

• ### A Uniquified Virtualization Approach to Hardware Security

Publication Year: 2017, Page(s):53 - 56
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Virtualization has well-known security advantages for operating systems and software, but current techniques do not address increasingly important hardware-security concerns. For widely deployed systems (e.g., Internet of Things) and safety-critical systems (e.g., defense and automobiles), protecting against device tampering is critical, but is often unavoidable due to the relative ease of side-ch... View full abstract»

• ### Public Key Authentication and Key Agreement in IoT Devices With Minimal Airtime Consumption

Publication Year: 2017, Page(s):1 - 4
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Computational complexity of public key cryptography over sensor nodes is not anymore a blocking concern in modern devices which natively (and efficiently) support elliptic curve cryptography. The problem has rather shifted toward the significant airtime consumption required to exchange multiple messages and certificates so as to perform authentication and key agreement. This letter addresses such ... View full abstract»

• ### Wearable Camera- and Accelerometer-Based Fall Detection on Portable Devices

Publication Year: 2016, Page(s):6 - 9
Cited by:  Papers (3)
| | PDF (506 KB) | HTML

Robust and reliable detection of falls is crucial especially for elderly activity monitoring systems. In this letter, we present a fall detection system using wearable devices, e.g., smartphones, and tablets, equipped with cameras and accelerometers. Since the portable device is worn by the subject, monitoring is not limited to confined areas, and extends to wherever the subject may travel, as opp... View full abstract»

• ### Tactics to Directly Map CNN Graphs on Embedded FPGAs

Publication Year: 2017, Page(s):113 - 116
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Deep convolutional neural networks (CNNs) are the state-of-the-art in image classification. Since CNN feed forward propagation involves highly regular parallel computation, it benefits from a significant speed-up when running on fine grain parallel programmable logic devices. As a consequence, several studies have proposed field-programmable gate array (FPGA)-based accelerators for CNNs. However, ... View full abstract»

• ### Fast Energy Efficient Radix-16 Sequential Multiplier

Publication Year: 2017, Page(s):73 - 76
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We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., F) as two high (H) and low (L) components, such that F = 4H + L, H, L ∈ {0, 1, 2, 3} × X, where X denotes the multiplicand. The required hard 3X multiple is generated in a preliminary cycle to the advantage of reducing the cycle time of the main iteration. Two radix-16 carry-save adders ... View full abstract»

• ### Mobile Application to Detect Induction Motor Faults

Publication Year: 2017, Page(s):117 - 120
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An Android-based application has been developed which can convert any mobile phone with inbuilt accelerometer into a squirrel cage induction motor (SCIM) fault diagnosis tool. To detect the faults, the mobile phone needs to be attached to the motor, and the application will record the motor vibration signal using the inbuilt accelerometer. After the recording, the faults are detected by locating t... View full abstract»

• ### Arduino Debugger

Publication Year: 2016, Page(s):85 - 88
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This letter describes our source-level debugger for Arduino which can be used to debug the code in Arduino using GNU debugger. The presented solution uses Eclipse as the visual front-end. It does not require any modification of the Arduino board or additional hardware; debug functionality is achieved by adding a program library to the user application. Standard functionality expected from a debugg... View full abstract»

• ### Real-Time Multiprocessor Scheduling Algorithm Based on Information Theory Principles

Publication Year: 2017, Page(s):93 - 96
| | PDF (612 KB) | HTML

Reducing job migrations is essential for any global multiprocessor scheduling algorithm. In this letter, we present a global, dynamic-priority, laxity-based algorithm that reduces the number of migrations on multiprocessor embedded systems by leveraging information theory principles. A simplification of the proposed scheduling theory is presented to reduce the overhead caused by using information ... View full abstract»

• ### An instruction-level quality-aware method for exploiting STT-RAM read approximation techniques

Publication Year: 2017, Page(s): 1
| | PDF (580 KB)

Although the read disturb STT-RAM approximation technique improves performance, it consists of an approximate read plus an approximate write both at the same time. So it may degrade the application Quality of Result (QoR) considerably. On the other hand, the incorrect read decision approximation technique improves power without corrupting the stored data. We adopt an opportunity study for instruct... View full abstract»

• ### SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems

Publication Year: 2017, Page(s):109 - 112
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This letter proposes a system architecture for a scalable software-assisted memory (SAM) hierarchy for emerging manycore embedded systems. Our SAM hierarchy overcomes the coherence overhead and inflexibility of purely hardware-managed memory hierarchies in adapting to variable workloads. Our preliminary results show opportunities for energy saving and performance improvement through: 1) a hybrid s... View full abstract»

• ### Open Challenges for Probabilistic Measurement-Based Worst-Case Execution Time

Publication Year: 2017, Page(s):69 - 72
| | PDF (117 KB) | HTML

The worst-case execution time (WCET) is a critical parameter describing the largest value for the execution time of programs. Even though such a parameter is very hard to attain, it is essential as part of guaranteeing a real-time system meets its timing requirements. The complexity of modern hardware has increased the challenges of statically analyzing the WCET and reduced the reliability of pure... View full abstract»

• ### Dynamic Alternation of Huffman Codebooks for Sensor Data Compression

Publication Year: 2017, Page(s):81 - 84
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Signal compression is crucial for reducing the amount of communication, and hence power consumption of wireless sensors. Lossless compression techniques, such as Huffman coding, are often used in healthcare applications since they do not compromise the integrity of vital signals. Techniques that adapt to changing signal patterns have been proposed. However, most of them involve significant computa... View full abstract»

• ### Structure-Aware Linear Solver for Realtime Convex Optimization for Embedded Systems

Publication Year: 2017, Page(s):61 - 64
| | PDF (444 KB) | HTML

With the increasing sophistication in the use of optimization algorithms such as deep learning on embedded systems, the convex optimization solvers on embedded systems have found widespread use. This letter presents a novel linear solver technique to reduce the run-time of convex optimization solver by using the property that some parameters are fixed during the solution iterations of a solve inst... View full abstract»

• ### Securing Hardware Accelerators: a New Challenge for High-Level Synthesis (Perspective Paper)

Publication Year: 2017, Page(s): 1
| | PDF (933 KB)

High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized System-on-Chip (SoC) architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applie... View full abstract»

• ### Fast Content Updating Algorithm for an SRAM based TCAM on FPGA

Publication Year: 2017, Page(s): 1
| | PDF (204 KB)

SRAM-based TCAM, an alternative to traditional TCAM, where inclusion of SRAM improves the memory access speed, scalability, cost, and storage density compared to conventional TCAM. In order to confidently use the SRAM-based TCAMs in application, an update module is essential. The update module replaces the old TCAM contents with fresh contents. This paper proposes a fast update mechanism for an SR... View full abstract»

• ### Data Reduction in Sensor Networks: Performance Evaluation in a Real Environment

Publication Year: 2017, Page(s):101 - 104
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Data reduction is an effective technique for energy saving in wireless sensor networks. It consists on reducing sensing and transmitting data while conserving a high quality of collected information. In this letter, we propose an online data reduction model based on Kruskal-Wallis test that allows sensor nodes to adapt their sensing rates based on the data variance. Then, we propose a local aggreg... View full abstract»

• ### Parallel and Pipelined 2D Median Filter Architecture

Publication Year: 2017, Page(s): 1
| | PDF (1488 KB)

The existing two dimensional median filters in the literature are computationally intensive. It is proposed to optimally reduce the amount of data handled at the architecture level realization of the basic median filtering operation on images. The proposed architecture reads 4 pixels at a time in the input image, 4 pixels forming a word on a 32 bit hardware processing system; the subsequent proces... View full abstract»

• ### A Taxonomy of General Purpose Approximate Computing Techniques

Publication Year: 2017, Page(s): 1
| | PDF (307 KB)

Approximate computing is the idea that systems can gain performance and energy efficiency if they expend less effort on producing a “perfect” answer. Approximate computing techniques propose various ways of exposing and exploiting accuracy–efficiency trade-offs. We present a taxonomy that classifies approximate computing techniques according to salient features: visibility, de... View full abstract»

• ### A Compact Portable Microwave Life-Detection Device for Finding Survivors

Publication Year: 2016, Page(s):10 - 13
Cited by:  Papers (1)
| | PDF (1370 KB) | HTML

In this letter, an ultra-sensitive compact portable microwave life-detection device is introduced and implemented with promising results. By utilizing Doppler effect-based systems, vital signs such as heartbeats and breathing can be detected and can be used for finding survivors under earthquake rubble, injured soldiers on battlefields and as lie detection device. This device is tested in both sim... View full abstract»

• ### Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Publication Year: 2015, Page(s):15 - 18
Cited by:  Papers (14)
| | PDF (903 KB) | HTML

A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping u... View full abstract»

• ### Security-Aware Modeling and Efficient Mapping for CAN-Based Real-Time Distributed Automotive Systems

Publication Year: 2015, Page(s):11 - 14
Cited by:  Papers (2)
| | PDF (491 KB) | HTML

Security has become a critical issue for automotive electronic systems. To protect against attacks, security mechanisms have to be applied, but the overhead of those mechanisms may impede system performance and cause violations of design constraints. To remedy this problem, we proposed an integrated mixed integer linear programming (MILP) formulation that is the first to address both security and ... View full abstract»

• ### Multipliers with Approximate 4-2 Compressors and Error Recovery Modules

Publication Year: 2017, Page(s): 1
| | PDF (917 KB)

Approximate multiplication is a common operation used in approximate computing methods for high performance and low power computing. Power-efficient circuits for approximate multiplication can be realized with an approximate 4-2 compressor. This letter presents a novel design that uses a modification of a previous approximate 4-2 compressor design and adds an error recovery module. The proposed de... View full abstract»

• ### Condition Codes Evaluation on Dynamic Binary Translation for Embedded Platforms

Publication Year: 2017, Page(s):89 - 92
| | PDF (566 KB) | HTML

A widely recognized issue when implementing dynamic binary translation is the condition codes (CCs) or flag bits emulation. The authors in the literature have approached this problem with software optimization techniques based on dataflow analysis, instruction set architecture (ISA) extensions and additional dedicated hardware, i.e., field-programmable gate array. We introduce a novel technique to... View full abstract»

• ### The IoT energy challenge: A software perspective

Publication Year: 2017, Page(s): 1
| | PDF (347 KB)

The Internet of Things (IoT) sparks a whole new world of embedded applications. Most of these applications are based on deeply embedded systems that have to operate on limited or unreliable sources of energy, such as batteries or energy harvesters. Meeting the energy requirements for such applications is a hard challenge, which threatens the future growth of the IoT. Software has the ultimate cont... View full abstract»

• ### A 64 kB Approximate SRAM Architecture for Low-Power Video Applications

Publication Year: 2017, Page(s): 1
| | PDF (14161 KB)

A voltage-scalable SRAM architecture suitable for video applications where energy can be traded with output signal quality is presented. The proposed 6T SRAM architecture uses three supply voltages to improve the static noise margin during read and write modes and also reduces leakage current in retention mode, hence, it allows aggressive supply voltage scaling for low power multimedia application... View full abstract»

• ### ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

Publication Year: 2014, Page(s):41 - 44
Cited by:  Papers (23)
| | PDF (440 KB) | HTML

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We... View full abstract»

• ### CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems

Publication Year: 2017, Page(s):77 - 80
| | PDF (926 KB) | HTML

Real-time systems have an increasing demand for predictable performance. Only recently novel models and analyses were proposed that make the performance benefits of runtime-reconfigurable architectures accessible for optimized worst-case execution time (WCET) guarantees. However, the implicit assumption in these works is that the process of reconfiguration itself complies with execution time guara... View full abstract»

• ### JTAG Fault Injection Attack

Publication Year: 2017, Page(s): 1
| | PDF (175 KB)

Fault injection attacks are wide spread in the domain of smart cards and microcontrollers but have not been yet democratized on complex embedded microprocessors such as system on chip (SoC) that can be found in smart phones, tablets and automotive systems. The main explanation is the difficulty involved in injecting a fault at the right place and at the right time to make these attacks effective o... View full abstract»

• ### HypAp: A Hypervolume-Based Approach for Refining the Design of Embedded Systems

Publication Year: 2017, Page(s):57 - 60
| | PDF (384 KB) | HTML

Designing complex embedded systems requires simultaneous optimization of multiple system performance metrics that can be addressed by applying Pareto-based multiobjective optimization techniques. At the end of this type of optimization process, designers always face Pareto fronts (PFs) including a large number of near-optimal solutions from which selecting the most proper system implementation is ... View full abstract»

• ### Motion Noise Cancelation in Heartbeat Sensing using Accelerometer and Adaptive Filter

Publication Year: 2015, Page(s):101 - 104
Cited by:  Papers (1)
| | PDF (762 KB) | HTML

This letter focuses on suppressing the motion artifact of wrist photoplethysmographic heart rate signals using an accelerometer based adaptive filter. Monitoring of the heart signal can offer important insights with regard to health and wellness. The objective of the experiment conducted here is to recover the distorted signal resulting from body movement while measuring the heart rate signal noni... View full abstract»

• ### A Security Layer for Smartphone-to-Vehicle Communication Over Bluetooth

Publication Year: 2013, Page(s):34 - 37
Cited by:  Papers (1)
| | PDF (528 KB) | HTML

Modern vehicles are increasingly being interconnected with computer systems, which collect information both from vehicular sources and Internet services. Unfortunately, this creates a nonnegligible attack surface, which extends when vehicles are partly operated via smartphones. In this letter, a hierarchically distributed control system architecture which integrates a smartphone with classical emb... View full abstract»

• ### Subleq $_circleddash$ : An Area-Efficient Two-Instruction-Set Computer

Publication Year: 2017, Page(s):33 - 36
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Applications with strict resource/power constraints demand the research and development of area-efficient processor designs that deliver reasonably good performance with small circuit area. While the ARM and RISC-V instruction set architecture (ISAs) are lightweight alternatives to ×86, they nevertheless consume considerable circuit area and power. In this letter, we return to a fundamental... View full abstract»

• ### A Novel Micro-Architecture Using a Simplified Logistic Map for Embedded Security

Publication Year: 2017, Page(s):41 - 44
| | PDF (317 KB) | HTML

A novel scheme for the introduction of chaos-based security into embedded systems at an architectural (hardware) level is presented in this letter. The logistic map is simplified for use in resource-constrained microcontrollers in the encryption of digital data through interface protocols like SPI etc. This letter, as an example, presents an outline of the registers and their associated logic for ... View full abstract»

• ### Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation

Publication Year: 2016, Page(s):81 - 84
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The IEEE 1666-2011 standard defines SystemC based on traditional discrete event simulation (DES) and sequential co-routine semantics, despite explicit parallelism in the model and ample parallel processor cores available in today's host computers. In order to evolve the SystemC standard toward faster parallel DES, substantial hurdles must be overcome. This letter identifies seven obstacles in the ... View full abstract»

• ### Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory

Publication Year: 2016, Page(s):57 - 60
| | PDF (613 KB) | HTML

Memory management on many-core architectures is a major challenge for improving the overall system performance. Memory resources are distributed over nodes for faster local accesses. Dynamic workloads heavily depend on memory requests and inefficient memory management leads to severe bottlenecks and performance degradation. In this paper, we focus on optimizing dynamic memory allocation on such pl... View full abstract»

• ### A New XOR-Free Approach for Implementation of Convolutional Encoder

Publication Year: 2016, Page(s):22 - 25
| | PDF (573 KB) | HTML

This letter presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolutional Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF(2), which consumes a significant amount of dynamic power. The proposed approach completely removes the XOR-processing operation of a chosen nonsystematic, feed-forward generator polynomial and... View full abstract»

• ### Synergistic Approximation of Computation and Memory Subsystems for Error-Resilient Applications

Publication Year: 2017, Page(s):21 - 24
| | PDF (671 KB) | HTML

Approximate computing is a new design paradigm that exploits the intrinsic error resilience exhibited by emerging applications to significantly improve their energy efficiency and performance. Prior work in this domain has proposed approximation techniques targeting either the computational subsystem or the memory subsystem. For the first time, this letter proposes a methodology to perform synergi... View full abstract»

• ### A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters

Publication Year: 2017, Page(s):125 - 128
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The instruction memory hierarchy plays a critical role in performance and energy efficiency of ultralow-power (ULP) processors for the Internet-of-Things (IoT) end-nodes. This is mainly due to the extremely tight power envelope and area budgets, which imply small instruction-caches (I-Cache) operating at very low supply voltages (near-threshold). The challenge is aggravated by the fact that multip... View full abstract»

• ### Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip

Publication Year: 2015, Page(s):31 - 34
Cited by:  Papers (8)
| | PDF (791 KB) | HTML

This letter analyses and compares on-chip interfaces for hardware/software communications in the Zynq-7000 all programmable systems-on-chip. Many experiments were carried out to evaluate the exchange of data between the processing system and the programmable logic through general-purpose and high-performance ports; the experiments were conducted for both standalone and Linux applications. The resu... View full abstract»

• ### A Reactive and Adaptive Data Flow Model for Network-of-System Specification

Publication Year: 2017, Page(s):121 - 124
| | PDF (208 KB) | HTML

With embedded systems being increasingly networked, appropriate models of computation and communication are needed for specification of such networks-of-systems. Traditional dataflow models have shown their usefulness in analyzing isolated systems. However, these models cannot express the inherent requirements of connected applications, such as dynamic behavior associated with network losses and r... View full abstract»

• ### Hardware-Assisted Detection of Malicious Software in Embedded Systems

Publication Year: 2012, Page(s):94 - 97
Cited by:  Papers (15)
| | PDF (385 KB) | HTML

One of the critical security threats to computer systems is the execution of malware or malicious software. Several intrusion detection systems have been proposed which perform detection analysis in the software using the audit files generated by the operating system. Software-based solutions to this problem are relatively slow, so these techniques can be used forensically, but not in real-time to... View full abstract»

• ### LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

Publication Year: 2017, Page(s):29 - 32
| | PDF (353 KB) | HTML

Binary content-addressable memory (BiCAM) is a popular high speed search engine in hardware, which provides output typically in one clock cycle. But speed of CAM comes at the cost of various disadvantages, such as high latency, low storage density, and low architectural scalability. In addition, field-programmable gate arrays (FPGAs), which are used in many applications because of its advantages, ... View full abstract»

• ### Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders

Publication Year: 2017, Page(s): 1
| | PDF (287 KB)

In this paper, we present a novel methodology to calculate the Arithmetic Error Rate (AER) for deterministic approximate adder architectures where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder int... View full abstract»

• ### Data Archival to SD Card Via Hardware Description Language

Publication Year: 2011, Page(s):105 - 108
Cited by:  Papers (3)
| | PDF (482 KB) | HTML

The main objective of this letter is to present the design of an efficient, real-time data archival system to a secure digital flash memory card via reconfigurable hardware. The data access from the SD card is implemented completely using Verilog and hence, there is no use of any microcontroller or on-chip general purpose processors. And since the complete design is a single-purpose system, no ext... View full abstract»

• ### NoC-Based Protection for SoC Time-Driven Attacks

Publication Year: 2015, Page(s):7 - 10
Cited by:  Papers (10)
| | PDF (647 KB) | HTML

Systems-on-chip (SoCs) based on many core architectures can be attacked. Malicious processes can infer secrets from on-chip sensible traffic by evaluating the degradation on their communication performance. Such a threat rises from the resource sharing. In order to avoid such time-driven attacks, the network-on-chip (NoC) can integrate mechanisms to isolate different communication flows. In this l... View full abstract»

• ### A Flexible Decision-Making Mechanism Targeting Smart Thermostats

Publication Year: 2017, Page(s):105 - 108
| | PDF (922 KB) | HTML

Buildings are immensely energy-demanding and are expected to consume even more in the near future. The operation of cooling/heating mechanisms highly contribute to this parameter, since nonoptimal configuration at temperature set-points usually leads to increased energy cost, as well as violations at occupant’s thermal comfort. In this letter, we introduce a flexible decision-making mechani... View full abstract»

## Aims & Scope

The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

## Meet Our Editors

EDITOR-IN-CHIEF
Sri Parameswaran
School of Computer Science and Engineering
University of New South Wales

DEPUTY EDITOR-IN-CHIEF
Tulika Mitra
School of Computing
National University of Singapore