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Electronic Computers, IEEE Transactions on

Popular Articles (December 2014)

Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
  • 1. A Suggestion for a Fast Multiplier

    Page(s): 14 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (723 KB)  

    It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ¿sec, and quotients in 3 ¿sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer. View full abstract»

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  • 2. Geometrical and Statistical Properties of Systems of Linear Inequalities with Applications in Pattern Recognition

    Page(s): 326 - 334
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    This paper develops the separating capacities of families of nonlinear decision surfaces by a direct application of a theorem in classical combinatorial geometry. It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes. Applying these ideas to the vertices of a binary n-cube yields bounds on the number of spherically, quadratically, and, in general, nonlinearly separable Boolean functions of n variables. It is shown that the set of all surfaces which separate a dichotomy of an infinite, random, separable set of pattern vectors can be characterized, on the average, by a subset of only 2d extreme pattern vectors. In addition, the problem of generalizing the classifications on a labeled set of pattern points to the classification of a new point is defined, and it is found that the probability of ambiguous generalization is large unless the number of training patterns exceeds the capacity of the set of separating surfaces. View full abstract»

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  • 3. Characteristics of Microstrip Transmission Lines

    Page(s): 185 - 193
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2176 KB)  

    Equations are developed which accurately describe the characteristic impedance and signal propagation delay for narrow microstrip transmission lines. Differences in signal propagation delay for microstrip, strip line, and coaxial cables are compared as a function of dielectric constant. The characteristic impedance equation is verified through comparison with experimental results for impedance values from 40 to 150 ohms. The sensitivity of characteristic impedance to variations in physical parameters, such as dielectric constant, line width, and board thickness, is presented. Finally the equation is shown to yield exceptionally accurate results when the inherent inaccuracies of the physical measurements are considered. View full abstract»

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  • 4. On the Connection Assignment Problem of Diagnosable Systems

    Page(s): 848 - 854
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    This paper treats the problem of automatic fault diagnosis for systems with multiple faults. The system is decomposed into n units u1, u2, . . . , un, where a unit is a well-identifiable portion of the system which cannot be further decomposed for the purpose of diagnosis. By means of a given arrangement of testing links (connection assignment) each unit of the system tests a subset of units, and a proper diagnosis can be arrived at for any diagnosable fault pattern. Methods for optimal assignments are given for instantaneous and sequential diagnosis procedures. View full abstract»

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  • 5. Analysis of Programs for Parallel Processing

    Page(s): 757 - 763
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    A set of conditions are described which determine whether or not two successive portions of a given program can be performed in parallel and still produce the same results. The conditions are general and can be applied to sections of the program of arbitrary size. The conditions are interesting because of the light they shed on the structure of programs amenable to parallel processing and the memory organization of a multi-computer system. View full abstract»

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  • 6. Apictorial Jigsaw Puzzles: The Computer Solution of a Problem in Pattern Recognition

    Page(s): 118 - 127
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    This paper describes the development of a procedure that enables a digital computer to solve ``apictorial'' jigsaw puzzles, i.e., puzzles in which all pieces are uniformly gray and the only available information is the shape of the pieces. The problem was selected because it provided an excellent vehicle to develop computer techniques for manipulation of arbitrary geometric patterns, for pattern identification, and for game solving. The kinds of puzzles and their properties are discussed in detail. Methods are described for characterizing and classifying piece contours, for selecting and ordering pieces that are ``most likely'' to mate with a given piece, for determining likelihood of fit, for overcoming ambiguities, and for evaluation of the progressive puzzle assembly. An illustration of an actual computer solution of a puzzle is given. View full abstract»

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  • 7. Crosstalk (Noise) in Digital Systems

    Page(s): 743 - 763
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    As digital system speeds increase and their sizes diminish, it becomes increasingly important to understand the mechanism of signal crosstalk (noise) in interconnections between logic elements. The worst case is when two wires run parallel for a long distance. Past literature has been unsuccessful in explaining crosstalk between parallel wires above a ground plane, because it was assumed that only one signal propagation velocity was involved. This paper proves that a signal introduced at one end of a printed wire above a ground plane in the presence of a second parallel (passive) wire must break up into two signals traveling at different velocities. The serious crosstalk implications are examined. The new terms slow crosstalk (SX), fast crosstalk (FX) and differential crosstalk (DX) are defined. View full abstract»

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  • 8. The Automatic Speech Recognition System for Conversational Sound

    Page(s): 835 - 846
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    This paper describes the method and the system investigated to solve the problem encountered in the automatic recognition of speech sound. From research in the automatic analyzer of speech sound, a monosyllable recognition system was constructed in which the phoneme is used as the basic recognition unit. Recently this system has been developed to accept the conversational speech sound with unlimited vocabulary. The mechanical recognition of conversational speech sound requires two basic operations. One is the segmentation of the continuous speech sound into several discrete intervals (or segments), each of which may be thought to correspond to a phoneme, and the other is the pattern recognition of such segments. For segmentation, by defining two criteria, ``stability'' and ``distance,'' the properties of the time pattern obtained by the analysis of input speech sound may be examined. The principle of the recognition is based on the mechanism of the articulation in our speech organ. Corresponding to this, the machine has the functions called phoneme classification, vowel analysis and consonant analysis. A conversational speech recognition system with the phonetic contextual approach is also applied to the vowel recognition where the time pattern of input speech is matched with the stored standard patterns in which the phonetic contextual effects are taken into consideration. The time pattern which has great variety may be effectively expressed by the new representation of ``sequential pattern'' and ``weighting pattern.'' View full abstract»

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  • 9. A Theory of Adaptive Pattern Classifiers

    Page(s): 299 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1535 KB)  

    This paper describes error-correction adjustment procedures for determining the weight vector of linear pattern classifiers under general pattern distribution. It is mainly aimed at clarifying theoretically the performance of adaptive pattern classifiers. In the case where the loss depends on the distance between a pattern vector and a decision boundary and where the average risk function is unimodal, it is proved that, by the procedures proposed here, the weight vector converges to the optimal one even under nonseparable pattern distributions. The speed and the accuracy of convergence are analyzed, and it is shown that there is an important tradeoff between speed and accuracy of convergence. Dynamical behaviors, when the probability distributions of patterns are changing, are also shown. The theory is generalized and made applicable to the case with general discriminant functions, including piecewise-linear discriminant functions. View full abstract»

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  • 10. Signal Flow Graph Techniques for Sequential Circuit State Diagrams

    Page(s): 67 - 76
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    This paper considers the application of signal flow graph techniques to the problem of characterizing sequential circuits by regular expressions. It is shown that the methods of signal flow graph theory, with the proper interpretation, apply to state diagrams of sequential circuits. The use of these methods leads to a simple algorithm for obtaining a regular expression describing the behavior of a sequential circuit directly from its state diagram. View full abstract»

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  • 11. Improving Digital Computer Performance Using Residue Number Theory

    Page(s): 93 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1622 KB)  

    Residue arithmetic has the interesting characteristic that in multiplication, addition and subtraction any digit in the result is dependent only on its two corresponding operand digits. Consequently, for these operations, residue arithmetic is inherently faster than the conventional weighted arithmetics. A system design approach for exploiting the desirable characteristics of both residue and conventional number theory in digital computers is the principal topic of this paper. Criteria for selecting the moduli, and general techniques for implementing the residue arithmetic operations by simple modifications of conventional circuitry are described. A specific system with a conventional word length of 25 bits and a residue system with moduli 128, 127, 63 and 31 are treated in detail, showing that in comparison to the conventional mode of computation, residue arithmetic addition and subtraction are 3 times faster and multiplication is 12 times faster. As an example of the usefulness of the approach, the problem of solving systems of simultaneous linear equations is considered. It is shown that in obtaining solutions by residue arithmetic, the residue mode computation time approaches one sixth that required in the conventional mode as the equation systems become more complex. View full abstract»

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  • 12. Automatic Assignment of Computations in a Variable Structure Computer System

    Page(s): 755 - 773
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3040 KB)  

    The problem of optimal assignment of subcomputations of a computational task to autonomous computing structures of a variable structure computing system is investigated. In particular, it is desired to determine which computing structures should be constructed from the hardware inventory of the variable structure computing system and which subcomputations should be executed on which computing structures, and in what sequence, so as to minimize the total cost of computation (cost of restructuring of the system and the cost of the actual execution time). A successive approximation assigmnent procedure is formulated. The procedure requires representation of the computational task by a directed graph and an estimate of the number of traversals of each computational loop, as well as the branching probabilities of each conditional branching operation. Computer programs for automatic execution of the assignment procedure have been written. A numerical experiment on a problem from the area of the x-ray diffraction analysis of crystal structures indicates that the procedure is computationally practical, and also demonstrates that execution of the problem in a variable structure system leads to a considerable gain over a system of three modern high-speed general purpose computers. View full abstract»

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  • 13. Multiple Reflections on Pulse Signal Transmission Lines-Model for Computer Solution

    Page(s): 193 - 202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1526 KB)  

    A mathematical model for multiple reflections on lossless, distortionless signal transmission lines is developed for step changes in voltage or current at the source. The model is quite general and is valid for a source driving either one or two lines each loaded with an arbitrary number of discontinuities at arbitrary distances. It will give an exact solution for discontinuities and terminations which are purely resistive and allows for resistances of any size, none of which need be alike. Although an exact solution is valid only when the capacitances are negligible, a method is presented which will partially compensate for a capacitively distorted wave if the capacitive-characteristic resistance time constant is reasonably small compared to the transit time of the line. Considerations for digital computer simulation of the mathematical model are discussed and several examples including open backplane wiring comparing actual and computer results are given. The model and simulation are especially useful for lines which are not terminated in the characteristic impedance at the source or load end and also where modification of the model can be made to investigate reactive and nonlinear terminations. View full abstract»

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  • 14. Generation of Polynomial Discriminant Functions for Pattern Recognition

    Page(s): 308 - 319
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    A practical method of determining weights for crossproduct and power terms in the variable inputs to an adaptive threshold element used for statistical pattern classification is derived. The objective is to make it possible to realize general nonlinear decision surfaces, in contrast with the linear (hyperplanar) decision surfaces that can be realized by a threshold element using only first-order terms as inputs. The method is based on nonparametric estimation of a probability density function for each category to be classified so that the Bayes decision rule can be used for classification. The decision surfaces thus obtained have good extrapolating ability (from training patterns to test patterns) even when the number of training patterns is quite small. Implementation of the method, both in the form of computer programs and in the form of polynomial threshold devices, is discussed, and some experimental results are described. View full abstract»

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  • 15. Fortran

    Page(s): 382 - 385
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    The fundamental concepts of FORTRAN, the most widely used high-level, scientific programming language, are set forth and the significant characteristics are described in historical order from inception of FORTRAN in 1954 to the present time. The basic problem of how to get high quality programming from an-easy- to-write high-level language is emphasized. View full abstract»

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  • 16. Majority Gate Networks

    Page(s): 4 - 13
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    This paper presents methods for realizing simple threshold functions of n arguments by networks of k-input majority gates, where k≪n. An optimal network realization of the 5-argument majority function using 3-input majority gates is given, and it is then generalized by steps with realizations for the (2n-l)-argument majority function (where n = 3, 4, ...) using (2n-3)-input majority gates, and then for the (2n-1)-argument majority function using (2k-l)-input majority gates (where k≪n). In a final generalization an array network using (2k-l)-input majority gates introduced for the realization of an (m/n), ``simple,'' threshold function (where m = 1, 2, ...,n). The array network is then applied to the synthesis of arbitrary symmetric functions; in the latter synthesis a realization of ``adjustable logic'' is given where, by simple control of network connections, the same network can be made to compute any symmetric function. The specific networks for ``5 by 3's'' (5-argument majority function realized by a 3-input majority gate), ``7 by 5's'', and ``7 by 3's'' are the best known. View full abstract»

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  • 17. Synthesis of UP-DOWN Counters

    Page(s): 146 - 151
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    IN this paper we will describe an algorithm for the decomposition of UP-DOWN counters. The constituents of the decomposed counters will be UP-DOWN counters of small modulus and small amounts of combinatorial logic. The main advantage accruing from this decomposition technique is that only a small number of building blocks is required to build counters with any modulus. We will begin the discussion by developing analysis techniques for particular interconnections of UP-DOWN counters. Following this, a general technique for the synthesis of an UP-DOWN counter with any modulus will be given. Only binary and ternary UP-DOWN counters and a small amount of combinatorial logic will be required. View full abstract»

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  • 20. Parallel Processing in a Restructurable Computer System

    Page(s): 747 - 755
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    Pragmatic problem studies predict gains in computation speeds in a variety of computational tasks when executed on appropriate problem-oriented configurations of the variable structure computer. The economic feasibility of the system is based on utilization of essentially the same hardware in a variety of special purpose structures. This capability is achieved by programmed or physical restructuring of a part of the hardware. Existence of important classes of problems which the variable structure computer system promises to render practically computable, as well as use of the system for experiments in computer organization and for evaluation of new circuits and devices warrant construction of a variable structure computer. This paper describes the organization, programming, and hardware of a variable structure computer system presently under construction at UCLA. View full abstract»

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  • 21. Majority Gate Networks

    Page(s): 606 - 618
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    Some new procedures for synthetizing three-input majority gate networks have been described. Both a geometrical approach on the map of the assigned function and an algebraic procedure have been discussed. The geometrical methods give a number of different solutions and may lead to the simplest networks, but their use requires ingenuity. Therefore, some of the solutions suggested by the analysis of the maps have been translated into algebraic expressions, which may be easily used for automatic computation. The techniques described are applicable to any and all Boolean functions and lead to simple solutions. In fact, every function of n variables can be implemented by a network having (n-1) levels of gates, if n is odd, or n levels, if n is even, at the most. All the procedures are relatively simple and can be extended to the synthesis of networks of any type (m, t). View full abstract»

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  • 22. Correlation Method for Computing Sensitivity Functions on a High-Speed Iterative Analog Computer

    Page(s): 140 - 146
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    During successive high-speed iterative-analog-computer runs, the parameters a1, a2, . . ., am of a simulated dynamical system are perturbed by mutually orthogonal binary sequences of perturbations ¿ai = ±¿a. Each parameter perturbation remains constant during a full 1-ms analog-computer run. Simple correlation of the perturbed solution-sample sequences x(tk)+¿x(tk) with each parameter-perturbation sequence simultaneously produces approximations ¿x(tk)/¿ai to all the system sensitivity coefficients ¿x(t)/¿ai as the sampling time tkis automatically stepped. Note that correlation with binary variables requires no multipliers. The new technique is compared to the conventional method requiring separate sensitivity-equation setups for each sensitivity coefficient, and a simple example is presented. View full abstract»

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  • 23. The Effects of Interconnections on High-Speed Logic Circuits

    Page(s): 476 - 487
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    By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed. View full abstract»

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  • 24. Fault Detection in Redundant Circuits

    Page(s): 99 - 100
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    It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults. This is an additional reason (besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain valid for some types of redundancy which serve a useful purpose, such as the elimination of logic hazards in two-level circuits. View full abstract»

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  • 25. Internal State Assignments for Asynchronous Sequential Machines

    Page(s): 551 - 560
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    The paper presents three procedures for coding the internal states of asynchronous sequential switching circuits. Resulting codes insure that the circuit will function according to flow table specifications independent of variations in transmission delays within the circuit. The assignment methods produce codes that allow one to maximize the operating speed of the circuit and are applicable to completely or incompletely specified sequential machines. View full abstract»

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  • 26. Multi-threshold threshold elements

    Page(s): 45 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3905 KB)  

    A multi-threshold element is one in which several thresholds are used to separate the true inputs from the false inputs. Many circuit elements and configurations can be described by this model. An approach, based on conventional single-threshold threshold elements, is developed for the analysis and synthesis of multithreshold threshold elements. It is shown that the basic properties of such elements are similar to conventional threshold elements, and that k-threshold threshold-element realizability of an arbitrary n-variable Boolean function can be related to conventional threshold-element realizability of a related (n+k-1)-variable Boolean function. Foundations for two basically different methods for the synthesis of a single-element realization of an arbitrary Boolean function are developed, as are procedures for transforming such a realization into both two-level and multilevel loop-free networks of k-threshold threshold elements k??1. Every element in the networks has the identical weight vector for the independent variables, which is some-times desirable. The transformation technique is a useful approach to the synthesis of functions by networks of conventional threshold elements. It is proved that if the given function requires a k-threshold threshold element, then at least [k/2+I] conventional threshold elements in a two-level network or [1+log2 k] such elements in a multilevel network are required. Transformations are given for corresponding minimum-gate networks. Electronic-circuit realizations of multi-threshold elements and some logical-design applications of the multi-threshold approach to network design are discussed. The latter indicate that this approach can be easy to use and can result in economical realizations. View full abstract»

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  • 27. Sequential Logic and its Application to the Synthesis of Finite Automata

    Page(s): 786 - 791
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    Three logic functions are introduced, two of which are functions in two-variables, named sequential logic product and sequential logic sum, while the third, depending on only one variable, is termed sequential logic negation. An algebraic theory is developed for logic processes where time plays an essential part; the connection is pointed out between sequential logic and the algebraic theory of multiple-state finite automata. This connection finally leads to new methods of analysis, as well as of synthesis, for finite automata operating according to given sequential equations; these methods offer certain advantages over standard procedures. Results obtained are likely to be useful in the theory of digital computers. View full abstract»

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  • 28. Identification and Minimization of Linear Machines

    Page(s): 367 - 376
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    This paper is a study of linear machines and their submachines. Methods are presented for finding the reduced form of a given linear machine with or without fixed initial state. A technique is suggested for detecting whether a machine is linear or can be embedded as a submachine in a linear machine. In the latter case a state assignment is produced for the minimum linear realization. Encoded inputs and outputs are assumed, but given machines are not assumed reduced, nor are there any restrictions on the number of states in the given machine or in the linear realization. The method also detects machines that are linearly realizable when constants are available. The main results are that the reduced form of a linear machine is linear and that a linearly realizable machine with r-independent states has an r-dimensional realization. View full abstract»

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  • 29. Slave Memories and Dynamic Storage Allocation

    Page(s): 270 - 271
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    The use is discussed of a fast core memory of, say, 32000 words as a slave to a slower core memory of, say, one million words in such a way that in practical cases the effective access time is nearer that of the fast memory than that of the slow memory. View full abstract»

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  • 30. Design of an Accumulator for a General Purpose Computer

    Page(s): 570 - 574
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    This paper describes the logical design of an accumulator register for a general purpose digital computer. The only logic gates used are NOR gates and inverter gates and the sole storage device is a gated clocked flip-flop which takes the value on a single input line when the gate line is high. The accumulator register operates in conjunction with another register called the memory exchange register. The memory exchange register can be added to the accumulator, subtracted from the accumulator, ANDed with, and ORed with the accumulator; the result in each case being placed in the accumulator. The accumulator can also be shifted right or left. The problem of carry propagation during addition is alleviated by carry bridging. The accumulator circuitry has been made simpler by treating the operations to be performed collectively rather than individually, and by careful assignment of input-values to the storage devices. View full abstract»

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  • 31. The Cascade Multiplier

    Page(s): 243 - 247
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    A new principle and circuit for the generation of the product of two variables is described in which the required result is a linear combination of readily produced secondary variables. The product of two variables can be expanded in a series in which each term is derived from the preceding one and from an auxiliary variable by linear operations and by maximum and minimum selection. Two ``converted'' variables are associated with each term of the expansion. The product is equal to a linear combination of the converted variables plus the product of the last two converted variables. The range of variation of successive converted signals decreases by half so that the series converges by factors of ¿ per term. The exrpansion stands in direct correspondence with electronic multipliers which use linear elements and diode selection circuits. Only two sign-changers are required for four-quadrant operation. When used in conjunction with an ancillary four-quadrant multiplier, the cascade multiplier increases its accuracy by factors of 4, 16, 64,..., if 1, 2, 3, ..., stages are used. Alternatively, a sufficient number of stages provides a complete multiplier even without the use of an ancillary multiplier. Accuracies of the order of ±0.1 per cent are readily obtained and speed of response is high. View full abstract»

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  • 32. Minimal Square Rooting

    Page(s): 181 - 185
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    Binary square rooting algorithms which yield a root in a redundant representation using digits 1, ¿1, and 0 are analyzed, particularly those yielding a root in a representation in which the number of nonzero digits is minimal. An algorithm which may lead to any possible minimal representation of the square root is developed. View full abstract»

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  • 33. Computer-Aided Digital System Design and Analysis Using a Register Transfer Language

    Page(s): 730 - 737
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    This paper presents the results of an attempt to automate part of a formalized method of system design. Basic to this method are two languages, Boolean algebra and a register transfer language. From a Boolean algebra description a digital system can be constructed while the second language can be used in a step by step description of the execution of each instruction. To illustrate, a register transfer language is used to give a description of an adder considered as part of a digital system. This description is then translated into a set of Boolean equations. Next, the automation of this translation by using a syntax-directed compiler is explained. The compiler requires a syntactic description of register transfers. This description is given using a meta-language called Backus normal form. A Backus normal form description of Boolean equations that is used for translating Boolean equations into register transfers is also given; this translation process is called analysis. The feasibility of computer-aided design and analysis is thereby demonstrated. The computer-aided design method described in this paper, besides eliminating drudgery and error, would permit several system designs to be attempted and evaluated; a permanent record of the chosen system would also be available for future modifications, maintenance, and simulation. The analysis programs could be used to check the effect on the system of any changes made in the Boolean equations (or equivalently the logical diagrams) and the effect of any unused operation codes. View full abstract»

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  • 34. A Theory and Method for Correlation Analysis of Nonstationary Signals

    Page(s): 909 - 919
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    In this paper, a method is developed for obtaining cross-correlation functions and autocorrelation functions of signals which are generated by nonstationary processes. The theory of the method is based upon optimal approximation of the ensemble correlation function, when only one pair of signals is available for the correlation analysis. The use of the ensemble approximation approach allows the demonstration of the two uncertainties that always accompany correlation analysis of nonstationary signals. Moreover, this ensemble approximation approach makes possible the development of a mathematical synthesis procedure which specifies the optimal form of a realizable correlation analyzer for nonstationary signals. The synthesis procedure is described in detail for a specific but representative case and then is summarized for other cases. An experimental study has been performed which verifies the theory and demonstrates its effectiveness. The method is particularly suitable for analog and hybrid simulation. View full abstract»

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  • 35. Invertible Boolean Functions

    Page(s): 529 - 541
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    A Boolean function has an inverse when every output is the result of one and only one input. There are 2n! Boolean functions of n variables which have an inverse. Equivalence classes of these functions are sets of equivalent functions in the sense that they are identical under a group operation on the input and output variables. This paper counts through five variables the number of equivalence classes of invertible Boolean functions under the group operation of complementation, permutation, and complementation and permutation, linear transformations and affine transformations. Lower bounds are given which experimentally give an asymptotic approximation. A representative function is given of each of the 52 classes of invertible Boolean functions of three variables under complementation and permutation. These are divided into three types of classes, 21 self-inverting functions, three functions have an inverse in the same class and 14 pairs of functions, each function of the pair in a different class. The four representative functions under the affine transformation are self-invertible. View full abstract»

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  • 36. Generalization of Consensus Theory and Application to the Minimization of Boolean Functions

    Page(s): 446 - 456
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    Given two implicants of a Boolean function, we can, by performing their consensus, find a third implicant. This operation has been used for finding the prime implicants of a Boolean function. In this paper, the consensus is extended from two to any number of terms. A property of these generalized consensus relations leads to a systematic way of finding them. It is shown that any prime implicant of a Boolean function is a generalized consensus; therefore the algorithm for the determination of the consensus relations can be used for finding the prime implicants. This new method is simpler than the usual process of iterative consensus. It is also shown in this paper that consensus theory can be used for finding the minimal sums of a Boolean function. The methods are applicable for any Boolean function, with or without don't care conditions, with a single or a multiple output. View full abstract»

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  • 38. Synthesis of Error-Tolerant Counters Using Minimum Distance Three State Assignments

    Page(s): 359 - 366
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    It is shown that by using minimum distance three state assignments and considering error states when deriving the input equations, counters tolerant of a single error can be synthesized. Although one flip-flop in the counter might be in error, the other flip-flops will continue to sequence correctly. Thus acceptable sequencing continues with a malfunctioning unit present in the circuit. Because of the error correcting properties of the state assignment, the correct state of the counter can be recovered. A one-bit error introduced by noise or an intermittent malfunction will be automatically corrected. Failure occurs if more than one flip-flop is in error. Redundancy is incorporated as an inherent result of the initial design procedure rather than being included after a nonredundant working design is obtained. Instead of using any of the known methods of simplification of Boolean functions, the synthesis procedure involves the selection of a minimum number of terms which satisfy a concise set of distance and intersection properties. The selection procedure is intrinsically suitable for machine computation. Although specific logic units are discussed, it is believed that the concepts are general in nature and can be applied to any type of logic hardware. View full abstract»

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  • 39. Relations Between Pn Cycles and Stable Feedback Shift Registers

    Page(s): 375 - 378
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    In this paper a relationship among distinct Pn+1 cycles, distinct stable maximum transient feedback shift registers of order n+1, and stable feedback shift registers of order n will be presented. In the course of the discussion, two algorithms will be introduced. The first will provide a one-to-one mapping between distinct stable feedback shift registers of order n and distinct stable maximum-transient feedback shift registers of order n+1. The second will provide a one-to-one mapping between distinct maximum transient feedback shift registers of order n+1 and distinct Pn+1 cycles. As a corollary to these relationships, an enumeration of the stable feedback shift registers is obtained. View full abstract»

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  • 40. High Speed Binary Parallel Adder

    Page(s): 799 - 802
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    A study of the output of a heuristic computer program reveals two four-state binary Turing machines which yield the highest known score for four states in Rado's co-called "Busy Beaver" logical game. There is evidence which supports the conjecture that this score of 13 is the particular value of ¿(4), where ¿is a noncomputable integer function associated with this game. It is also conjectured that S(4) = 106, where S is another noncomputable function, the maximum shift number, of interest in Rado's study. Complete solution of the problem for four states has been reduced to a relatively small set of machines. View full abstract»

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  • 41. A Lower Bound of the Number of Threshold Functions

    Page(s): 926 - 929
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    Threshold functions are a class of Boolean Functions which have been studied for several years under different names such as majority functions, linearly separable functions, and linear input functions. View full abstract»

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  • 42. Algol

    Page(s): 377 - 381
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    After tracing the history of the development of ALGOL this paper discusses its current status as a candidate for adoption as an international standard. The main features of the language are then described and an example of ALGOL programming is provided and explained. View full abstract»

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  • 43. A Fast Analog Comparison for Hybrid Computation

    Page(s): 717 - 719
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    This paper describes the design of a new exceptionally fast analog comparator with digital output for hybrid computation. A wide-band dc amplifier with regenerative feedback permits high-speed comparator operation within 100 ns of zero crossing for all input rates of change between zero and 5×106 volts/second. Static hysteresis between ±10 mV and ±40 mV improves noise immunity. Drift is less than 25 microvolts per degree centigrade without chopper stabilization, which is optional. A simple two-transistor circuit provides both the regeneration and the digital output. View full abstract»

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  • 44. Logical Design of Ternary Switching Circuits

    Page(s): 19 - 29
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    A logical design theory for ternary voltage switching circuits is developed. The theory is based on familiar binary switching circuit elements and simplification methods. The theory thus leads to simple electronic realization. The basic system of ternary switching elements consists of function realizable by means of either diode gates or a single triode (transistor). Various simplification methods for combinational circuits are described, namely a map method and two algebraic methods. The first algebraic method is an adaptation of the Quine method for determining the prime implicants of a given binary function, and the second is a modification of the Scheinman binary method. View full abstract»

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  • 45. Lower Bounds of the Number of Threshold Functions and a Maximum Weight

    Page(s): 136 - 148
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    A lower bound on the number of threshold functions and a lower bound on the maximum of minimum weights of a threshold element are derived from a recursively constructed family of threshold elements. All threshold functions of n variables are difficult to construct for a general value of n, but it is shown that a large number of them can be constructed recursively from threshold functions of fewer variables. Schemes of such generation and related proper ties are discussed. Threshold functions generated in this way are so numerous that they constitute a constructive proof of a good lower bound on the number of threshold functions. By a similar procedure, we can derive a lower bound on the maximum of minimum weights of a threshold element. In this paper, discussion is limited to self-dual threshold functions, but this does not sacrifice generality, because any threshold function can be derived from a self-dual threshold function by assigning 1 or 0 to a certain variable. View full abstract»

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  • 47. The Minimization of TANT Networks

    Page(s): 18 - 38
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    A TANT network is a three-level network composed solely of AND-NOT gates (i.e., NAND gates) having only true (i.e. uncomplemented) inputs. The paper presents an algorithm for finding for any given Boolean function a least-cost (i.e. fewest number of gates) TANT network. The method used is similar to the Quine-McCluskey algorithm for two-level AND/OR networks. Certain functions realizable by input gates or second-level gates are preselected as candidates for possible use in an optimal network. This is analogous to the preselecting of prime implicants in two-level minimization. A network is then obtained by choosing a least-cost subset of the candidates which is adequate for realizing the function. This selection phase is analogous to the use of a prime implicant table in two-level minimization. In TANT minimization, however, an extension to a prime implicant table known as a CC-table must be used. The algorithm permits hand solution of typical four-and five-variable problems. A computer program has been written to handle more complex cases. View full abstract»

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  • 48. Computation of the Base Two Logarithm of Binary Numbers

    Page(s): 863 - 867
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    An approximation to the computation of the base two logarithm of a binary number, realized with binary circuitry, is described. It is known that the logarithm can be obtained approximately from the binary number itself by simple counting and shifting. A method for the reduction of the resulting approximation error by a factor six is given. The same principle can be used for further reduction of the error. The realization involving not only counting and shifting but also binary decision making and addition is described. Technical data about the performance of the constructed computer are given. View full abstract»

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  • 49. Figure of Merit of Electronic Switching Devices

    Page(s): 643 - 646
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    To specify the amplifying properties of various active electronic devices the gain-bandwidth product GNB is commonly used. The aim of this paper is to show that for active electronic (not electromagnetic) devices working in switching circuits, another figure of merit (analogous to the reciprocal of the gain-bandwidth product) could be derived from a simple model of an electronic switch. View full abstract»

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  • 50. On the Number of Distinct State Assignments for Synchronous Sequential Machines

    Page(s): 220 - 221
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    In an early paper [1], McCluskey and Unger counted the number of distinct state assignments for synchronous sequential machines. Their formula, however, does not account for all distinct state assignments when the memory function in a realization is performed by delay elements alone. This note amends their formula by establishing the conditions for its validity and by deriving the appropriate expression under other conditions. An example illustrating the effect of using the McCluskey-Unger formula in a case where it does not apply can be found in a recent paper by Dolotta and McCluskey [2]. In their paper, a procedure is proposed for selecting a state assignment that has an associated economical realization. Their method implicitly restricts the memory units to be delay elements, and some distinct state assignments are not considered. Consequently, a number of realizations are over-looked. A minor modification in the Dolotta-McCluskey algorithm is suggested so that all distinct state assignments are taken into account. In some cases this revised procedure results in a more economical realization than the unmodified one. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope