By Topic

# IEEE Journal of Solid-State Circuits

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Publication Year: 2010, Page(s):731 - 740
Cited by:  Papers (372)  |  Patents (9)
| | PDF (1463 KB) | HTML

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually... View full abstract»

• ### Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Publication Year: 2017, Page(s):127 - 138
Cited by:  Papers (2)
| | PDF (5284 KB) | HTML

Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. This is b... View full abstract»

• ### A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Publication Year: 2017, Page(s):1144 - 1162
| | PDF (8981 KB) | HTML

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Low 1/f DCO nois... View full abstract»

• ### A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

Publication Year: 2017, Page(s):1331 - 1344
| | PDF (3308 KB) | HTML

A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a π-type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Mu... View full abstract»

• ### A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

Publication Year: 2017, Page(s):1101 - 1110
| | PDF (4263 KB) | HTML

A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid analog and digital equalizations. The analog equalization is performed using two identical stages of continuous time linear equalizer, each hav... View full abstract»

• ### A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems

Publication Year: 2017, Page(s):1443 - 1449
| | PDF (2636 KB) | HTML

This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking ... View full abstract»

• ### A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

Publication Year: 2017, Page(s):1551 - 1562
| | PDF (3312 KB) | HTML

A high-speed 2b-1b/cycle two-step successive-approximation-register analog-to-digital converter (ADC) exploiting the passive residue transfer technique is reported. The removal of the residue amplifier results in savings in the time and power consumed by the residue transfer process. The kT/C noise and potential bandwidth mismatch associated with the passive residue transfer are analyzed and also ... View full abstract»

• ### A low-power low-noise CMOS amplifier for neural recording applications

Publication Year: 2003, Page(s):958 - 965
Cited by:  Papers (723)  |  Patents (65)
| | PDF (661 KB) | HTML

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier... View full abstract»

• ### A 94-GHz 4TX–4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package

Publication Year: 2017, Page(s):1245 - 1259
| | PDF (4576 KB) | HTML

A 94-GHz phased-array transceiver IC for frequency modulated continuous wave (FMCW) radar with four transmitters, four receivers, and integrated LO generation has been designed and fabricated in a 130-nm SiGe BiCMOS technology, and integrated into an antenna-in-package module. The transceiver, targeting gesture recognition applications for mobile devices, has been designed using phased-array techn... View full abstract»

• ### Design-Oriented Analysis for Miller Compensation and Its Application to Multistage Amplifier Design

Publication Year: 2017, Page(s):517 - 527
| | PDF (2248 KB) | HTML

A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes. The method predicts the nondominant poles of the Miller-compensated amplifiers in an intuitive manner, and it serves as a good supplement to the conventional analysis. The usage of DOA is verified by the various design examples given in this paper. Guided by DOA, a multis... View full abstract»

• ### A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier

Publication Year: 2017, Page(s):1412 - 1423
| | PDF (4017 KB) | HTML

A 6.78-MHz wireless power receiver using a 3-mode reconfigurable resonant regulating rectifier for resonant wireless power transfer is presented. The proposed receiver improves power conversion efficiency and reduces die area and off-chip components by achieving power conversion plus voltage regulation in one stage, using only four on-chip power transistors and one off-chip capacitor. Moreover, th... View full abstract»

• ### A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Publication Year: 2017, Page(s):1399 - 1411
| | PDF (5878 KB) | HTML

Design techniques to improve energy efficiency of serial link transceivers are presented. Power consumption is reduced by using: low-power clock generation, recovery, and distribution schemes; charge-based circuits to implement analog front-end and samplers/flip-flops; and a partially segmented voltage-mode (VM) output driver. An LC-oscillator based digital phase-locked loop (PLL) is used to gener... View full abstract»

• ### Voltage Mode Doherty Power Amplifier

Publication Year: 2017, Page(s):1295 - 1304
| | PDF (2592 KB) | HTML

This paper presents a new wideband Doherty amplifier technique that can achieve high efficiency while maintaining excellent linearity. By modifying a “forgotten” topology originally proposed by Doherty, a new Doherty amplifier architecture is realized with two voltage mode power amplifiers (PAs) and transformers, thus eliminating a narrowband impedance inverter. The voltage mode PA i... View full abstract»

• ### A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power

Publication Year: 2017, Page(s):1680 - 1686
| | PDF (3152 KB) | HTML

In this paper, we present a two-stage, four-way combined power amplifier (PA) operating in the 27-31-GHz frequency range in 180-nm SiGe BiCMOS technology. The output network of the PA employs spiral transformers and a microstrip T-combiner to realize low-loss two-way series, two-way parallel power combining. With the help of a lumped-element transformer model, we present a co-optimization techniqu... View full abstract»

• ### A Wideband Fully Integrated Software-Defined Transceiver for FDD and TDD Operation

Publication Year: 2017, Page(s):1274 - 1285
| | PDF (3419 KB) | HTML

Although there is much active research on software-defined radios (SDRs) with receive (RX) or transmit (TX) functionality, little work has been done on SDR transceivers supporting frequency division duplex (FDD). In this paper, we present a new circuit concept in which a distributed TX circuit cancels the transmitted signal at a reverse RX port through destructive interference while adding signal ... View full abstract»

• ### A 0.7-V 0.6- $\mu \text{W}$ 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

Publication Year: 2017, Page(s):1388 - 1398
| | PDF (2939 KB) | HTML

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relati... View full abstract»

• ### A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma$ -TDC for Low In-Band Phase Noise

Publication Year: 2017, Page(s):1885 - 1903
| | PDF (6026 KB)

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order View full abstract»

• ### A Multiphase Switched Capacitor Power Amplifier

Publication Year: 2017, Page(s):1320 - 1330
| | PDF (2597 KB) | HTML

This paper presents an all-digital multiphase switched capacitor power amplifier (MP-SCPA) implemented in a 130-nm CMOS. Quadrature architectures suffer reduced output power and efficiency owing to the combination of out-ofphase signals. The MP architecture reduces the phase difference between the basis vectors that are combined, and hence the output power and efficiency are greatly improved. Sixt... View full abstract»

• ### An 802.11a/b/g/n Digital Fractional- $N$ PLL With Automatic TDC Linearity Calibration for Spur Cancellation

Publication Year: 2017, Page(s):1210 - 1220
| | PDF (4160 KB) | HTML

A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to achieve wide detection range with fine resolution. The TDC is calibrated automatically utilizing the ramp signal generated from the fractional-N accumulator for optimal linearity. A digi-phase spur cancellation technique wi... View full abstract»

• ### A Digital Polar Transmitter With DC–DC Converter Supporting 256-QAM WLAN and 40-MHz LTE-A Carrier Aggregation

Publication Year: 2017, Page(s):1196 - 1209
| | PDF (4915 KB) | HTML

A digital polar transmitter is introduced using 9-b thermometer-coded uniform cells for wideband signal. By analyzing amplitude and phase paths impairment which causes both in-band and out-of-band distortions, a 960-MHz delay tuner is designed for precise amplitude and phase alignment. Furthermore, two digital pre-distortion algorithms for digital power amplifier (DPA) are implemented and compared... View full abstract»

• ### A Dynamic Zoom ADC With 109-dB DR for Audio Applications

Publication Year: 2017, Page(s):1542 - 1550
| | PDF (3552 KB) | HTML

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 i... View full abstract»

• ### A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

Publication Year: 2017, Page(s):623 - 633
| | PDF (2432 KB) | HTML

This paper describes an MOSFET-only voltage reference realized in 65-nm CMOS featuring a temperature coefficient (TC) of 5.6 ppm/°C from -40 °C to 125 °C, a power supply rejection ratio of 87 dB from dc up to 800 kHz (and 75 dB at 1 MHz), a minimum supply voltage of 0.8 V, and a power dissipation of 13 μW. These attributes are achieved by exploiting the zero-TC point of... View full abstract»

• ### A CMOS Passive LPTV Nonmagnetic Circulator and Its Application in a Full-Duplex Receiver

Publication Year: 2017, Page(s):1358 - 1372
| | PDF (4614 KB) | HTML

Recently, we demonstrated the first CMOS nonmagnetic nonreciprocal passive circulator based on N-path filters that uses time variance to break reciprocity. Here, the analysis of performance metrics, such as loss, isolation, linearity, and tuning range, is presented in terms of the design parameters. The analysis is verified by the measured performance of a 65-nm CMOS circulator prototype that exhi... View full abstract»

• ### A 28-GHz Phased-Array Receiver Front End With Dual-Vector Distributed Beamforming

Publication Year: 2017, Page(s):1230 - 1244
| | PDF (5188 KB) | HTML

This paper presents a 28-GHz four-channel phased-array receiver in 130-nm SiGe BiCMOS technology for fifth-generation cellular application. The phased-array receiver employs scalar-only weighting functions within each receive path and then global quadrature power combining to realize beamforming. We discuss both the theory and nonidealities of this architecture and then circuit design details for ... View full abstract»

• ### A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation

Publication Year: 2017, Page(s):1463 - 1478
| | PDF (11579 KB) | HTML

This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency enhancement into the deep power back-off (PBO) region. Moreover, we dynamically manipulate the PA load impedance trajectory that travels from the optimum output power (Pout) load impedance to the optimum efficiency load impedanc... View full abstract»

• ### A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Publication Year: 2014, Page(s):3091 - 3103
Cited by:  Papers (16)
| | PDF (3299 KB) | HTML

This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-ra... View full abstract»

• ### An AC Input Switching-Converter-Free LED Driver With Low-Frequency-Flicker Reduction

Publication Year: 2017, Page(s):1424 - 1434
| | PDF (7791 KB) | HTML

This paper presents a novel switching-converter-free ac-dc light-emitting diode (LED) driver with low-frequency-flicker reduction for general lighting applications. The proposed driving solution can minimize the system size as it enables the monolithic integration of the controller and power transistors while both the bulky off-chip electrolytic capacitors and magnetics are eliminated. Moreover, t... View full abstract»

• ### A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18- $\mu \text{m}$ CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications

Publication Year: 2017, Page(s):1479 - 1494
| | PDF (5392 KB) | HTML

This paper describes a short-range transceiver architecture using frequency-hopped sinusoidal OOK pulses. Since signal bandwidth does not necessarily have to satisfy >500 MHz requirement like conventional ultra-wideband (UWB) pulses, the proposed transceiver named as a very-wide band (VWB) transceiver offers degrees of freedom to choose an optimum operation duty cycle in terms of energy efficie... View full abstract»

• ### Design and Self-Calibration Techniques for Inductor-Less Millimeter-Wave Frequency Dividers

Publication Year: 2017, Page(s):1521 - 1541
| | PDF (5178 KB) | HTML

This paper presents several design techniques to widen the operating frequency range and increase the locking range of dynamic current-mode latch-based inductor-less millimeter-wave frequency dividers. A self-calibration technique is introduced to guarantee frequency locking over a wide frequency range with low-input amplitude and over process, voltage, and temperature variations, thereby optimizi... View full abstract»

• ### A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection

Publication Year: 2017, Page(s):1286 - 1294
| | PDF (2780 KB) | HTML

The modulated wideband converter receiver architecture leverages compressive sensing techniques to improve flexibility for cognitive radio applications. We present a prototype integrated circuit that adds signal reception to previously demonstrated signal detection. By refactoring the mixing sequence between signal detection and reception, we enable targeted reception and blocker rejection. We alg... View full abstract»

• ### An RF-Powered FDD Radio for Neural Microimplants

Publication Year: 2017, Page(s):1221 - 1229
| | PDF (4276 KB) | HTML

We present a radio system that could be used in millimeter-scale wireless neural implants. The system is RF-powered and demonstrates Mbps data rates required for neuromodulation and recording applications. The radio transmits at 58 Mb/s and receives at 2.5 Mb/s maximum data rates. The transceiver uses a duplexer to achieve full-duplex communication via frequency-division duplexing at 1.74 and 1.86... View full abstract»

• ### A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Publication Year: 2010, Page(s):1111 - 1121
Cited by:  Papers (235)  |  Patents (3)
| | PDF (1790 KB) | HTML

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-... View full abstract»

• ### A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS

Publication Year: 2017, Page(s):1091 - 1100
| | PDF (2097 KB) | HTML

This paper presents a power- and area-efficient 16-way time-interleaved (TI) analog-to-digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm CMOS. A voltage-time hybrid pipeline technique exploiting the comparator input-voltage-output-time dependency is reported to enhance the throughput of successive-approximation-register (SAR) ADCs. A reference-buffer-free cap... View full abstract»

• ### A High Dynamic-Range Neural Recording Chopper Amplifier for Simultaneous Neural Recording and Stimulation

Publication Year: 2017, Page(s):645 - 656
| | PDF (3513 KB) | HTML

Closed-loop neuromodulation is essential for the advance of neuroscience and for administering therapy in patients suffering from drug-resistant neurological conditions. Neural stimulation generates large artifacts at the recording sites, which easily saturate traditional recording front ends. This paper presents a neural recording chopper amplifier capable of handling in-band artifacts up to 40 m... View full abstract»

• ### A study of injection locking and pulling in oscillators

Publication Year: 2004, Page(s):1415 - 1424
Cited by:  Papers (552)  |  Patents (26)
| | PDF (808 KB) | HTML

Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated. View full abstract»

• ### A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC

Publication Year: 2015, Page(s):303 - 319
Cited by:  Papers (25)
| | PDF (4437 KB) | HTML

We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contras... View full abstract»

• ### In Vitro Multi-Functional Microelectrode Array Featuring 59 760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement, and Neurotransmitter Detection Channels

Publication Year: 2017, Page(s):1576 - 1590
| | PDF (7135 KB)

Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high-spatiotemporal resolution. To this end, we have developed a CMOS-based mic... View full abstract»

• ### A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC

Publication Year: 2017, Page(s):1953 - 1965
| | PDF (4008 KB)

An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time cha... View full abstract»

• ### A 46 $mu text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

Publication Year: 2017, Page(s):423 - 432
| | PDF (3585 KB) | HTML

A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them s... View full abstract»

• ### A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting

Publication Year: 2017, Page(s):357 - 370
| | PDF (2919 KB) | HTML

In this paper, a general embedding is proposed to boost the power gain of any device to the maximum achievable gain (Gmax), which is defined as the maximum theoretical gain of the device. Using a gain-plane based analysis, two linear-lossless-reciprocal embeddings are used to perform a movement from the coordinate of the transistor to the coordinate that corresponds to Gmax. ... View full abstract»

• ### A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) $P_{\mathrm {out}}$

Publication Year: 2017, Page(s):1495 - 1508
| | PDF (3466 KB) | HTML

This paper describes a sub-1-V 2.4-GHz ZigBee transmitter (TX) with scalable output power (Pout) and system efficiency. It features a function-reuse class-F topology unifying the digital-controlled oscillator (DCO) and power amplifier (PA), designated as DCO-PA. Unlike the existing current-reuse topologies that rely on transistor stacking, here the power consumption of the DCO and PA-dr... View full abstract»

• ### A 1–3 GHz Delta–Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

Publication Year: 2017, Page(s):1185 - 1195
| | PDF (5022 KB) | HTML

This paper presents a new fully digital architecture for an RF phase modulator with significantly improved phase resolution. The modulator utilizes 32 variable delay-lines in a delay-locked loop (DLL) configuration to provide 1-3 GHz operation with coarse 5-bit resolution. A 5-bit low-glitch multiplexer with accurate delay control on the control lines is used to select different taps of the DLL ac... View full abstract»

• ### A 174.3-dB FoM VCO-Based CT $\Delta \Sigma$ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS

Publication Year: 2017, Page(s):1940 - 1952
| | PDF (3935 KB)

This paper presents a high dynamic range (DR) power-efficient voltage-controlled oscillator (VCO)-based continuous-time $\Delta \Sigma$ modulator. It introduces a robust and low-power fully-digital phase extended quantizer that doubles the VCO quantizer resolution compared to a conventional XOR-based phase detector. A tri-le... View full abstract»

• ### A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

Publication Year: 2017, Page(s):1863 - 1875
| | PDF (6493 KB)

This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon-on-insulator process. A fully integrated simultaneous-switching switched-capacitor DC–DC converter supplies an application core using a clock from a free-running adaptive clock generator, achieving high system conversion ... View full abstract»

• ### A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device

Publication Year: 2002, Page(s):526 - 530
Cited by:  Papers (228)  |  Patents (9)
| | PDF (298 KB) | HTML

A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with Vthn ≈ |Vthp| ≈ 0.9 V at 0°C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 μA. A temperature coefficient of 15 ppm/°C from 0°C to 100°C is recorded aft... View full abstract»

• ### A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier

Publication Year: 2016, Page(s):1261 - 1273
| | PDF (4246 KB) | HTML

This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed b... View full abstract»

• ### A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers

Publication Year: 2017, Page(s):1915 - 1926
| | PDF (4964 KB)

This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necess... View full abstract»

• ### A 60-GHz Dual-Vector Doherty Beamformer

Publication Year: 2017, Page(s):1373 - 1387
| | PDF (5703 KB) | HTML

In this paper, we demonstrate a 60-GHz transmit beamformer implemented in 130-nm SiGe BiCMOS technology which includes a Doherty amplifier driven by a dual-vector phase rotator (DVR). In addition, a benchmarking circuit comprising another DVR followed by two class-AB amplifiers, each nearly identical to the carrier amplifier within the Doherty, is included which allows us to measure the Doherty im... View full abstract»

• ### An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

Publication Year: 2017, Page(s):903 - 914
| | PDF (3098 KB) | HTML

A precision-scalable processor for low-power ConvNets or convolutional neural networks is implemented in a 40-nm CMOS technology. To minimize energy consumption while maintaining throughput, this paper is the first to implement dynamic precision and energy scaling and exploit the sparsity of convolutions in a dedicated processor architecture. The processor's 256 parallel processing units achieve a... View full abstract»

• ### A 63-dB DR 22.5-MHz 21.5-dBm IIP3 Fourth-Order FLFB Analog Filter

Publication Year: 2017, Page(s):1977 - 1986
| | PDF (3249 KB)

In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active-RC/Active- $g_{m}$ -... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com