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Circuits, Devices and Systems, IEE Proceedings -

Popular Articles (November 2014)

Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
  • 1. CMOS transconductance amplifiers, architectures and active filters: a tutorial

    Page(s): 3 - 12
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    An updated version of a tutorial paper (see IEEE Circuits Devices Mag., vol. 2, no. 1, p. 20-32, 1985) on active filters using operational transconductance amplifiers (OTAs) is presented. The integrated circuit issues involved in active filters (using CMOS transconductance amplifiers) and the progress in this field in the last 15 years is addressed. CMOS transconductance amplifiers, nonlinearized and linearized, as well as frequency limitations and dynamic range considerations are reviewed. OTA-C filter architectures, current-mode filters, and other potential applications of transconductance amplifiers are discussed View full abstract»

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  • 2. Development of an electromagnetic micro-generator

    Page(s): 337 - 342
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (799 KB)  

    A design methodology for linear micro-generators is developed, and is applied to the design of a mm-scale electromagnetic micro-generator. The fabrication of a prototype device is also described using generally available microfabrication techniques, and the results of testing the device on a variable amplitude vibration source, in air and vacuum, are presented. The experimental results confirm the design rules and indicate how the generation of useful power levels might be achieved View full abstract»

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  • 3. Novel CMOS differential voltage current conveyor and its applications

    Page(s): 195 - 200
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    Novel CMOS realisations of a differential voltage current conveyor (DVCC) are described. These circuits are powerful building blocks, especially for applications demanding differential or floating inputs like impedance converter circuits and current mode instrumentation amplifiers. Applications suitable for VLSI are then considered by using the DVCC to realise a MOS transconductor and a continuous-time current mode MOSFET-C filter. PSpice simulations indicate the excellent performance of the proposed DVCC and of its circuit applications View full abstract»

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  • 4. Low-voltage low-power CMOS full adder

    Page(s): 19 - 24
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented View full abstract»

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  • 5. Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

    Page(s): 573 - 578
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched -capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided. View full abstract»

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  • 6. Spintronics device concepts

    Page(s): 312 - 322
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1339 KB)  

    Spin-dependent phenomena in semiconductors may lead to devices with new or enhanced functionality, such as polarised solid-state light sources (spin light-emitting diodes), novel microprocessors and sensitive biological and chemical sensors. The realisation of robust semiconductor spin-device technology requires the ability to control the injection, transport and detection of polarised carriers, and to manipulate their density by a field gating. The absence of Si-based or room-temperature dilute magnetic semiconductors has subdued the initial excitement over semiconductor spintronics, but recent reports demonstrate that progress is far from dormant. The authors give examples of a number of different spin-device concepts for polarised light emission, spin field-effect transistors and nanowire sensors. It is important to re-examine some of the earlier concepts for spintronics devices, such as the spin field-effect transistor, to account for the presence of the strong magnetic field which has deleterious effects. In some of these cases, the spin device appears to have no advantage relative to the conventional charge-control electronic analogue. There have been demonstrations of device-type operation in structures based on GaMnAs and InMnAs at low temperatures. The most promising materials for room-temperature polarised light emission are thought to be GaN and ZnO, but results to date on realising such devices have been disappointing. The short spin-relaxation time observed in GaN/InGaN heterostructures probably results from the Rashba effect. Possible solutions involve either cubic phase nitrides or the use of additional stressor layers to create a larger spin-splitting, to get polarised light emission from these structures, or to look at alternative semiconductors and fresh device approaches. View full abstract»

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  • 7. CMOS floating active inductor and its applications to bandpass filter and oscillator designs

    Page(s): 42 - 48
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A CMOS fully differential floating active inductor is realised by exploiting the intrinsic capacitance of the transistor. This technique allows the simulated inductor to operate closer to the fT, of the technology. Simulation results using SpectreRF with AMS 0.8 μm CMOS process show a self resonant frequency over 1 GHz, and independent tuning of the inductance and the series resistance values. The floating active inductor has been employed in the design of a fourth-order 100 MHz IF bandpass filter and a second-order RF tunable oscillator to demonstrate its performance View full abstract»

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  • 8. Colour histogram content-based image retrieval and hardware implementation

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (350 KB)  

    With the ongoing development of multimedia technology, the number of information systems containing image retrieval functions is increasing rapidly. Techniques of colour histogram content-based image retrieval are compared in terms of speed and efficiency, and a modified approach based on a composite colour image histogram processing is introduced. The proposed approach is fast and provides results comparable to those of much slower algorithms. Furthermore, a novel pipelined hardware structure has been designed and implemented on an FPGA, to increase the operation speed and make the technique suitable for real-time applications. The typical clock frequency of this device is 35 MHz and it can perform over 50 comparisons of 640×480-pixel images per second View full abstract»

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  • 9. Solving the two capacitor paradox through a new asymptotic approach

    Page(s): 227 - 231
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (391 KB)  

    Closing an ideal switch between two passive linear lumped time-invariant capacitors with different initial voltages gives rise to an apparent paradox. A part of the total energy stored in the two capacitors suddenly vanishes, but, seemingly, the switch cannot account for this loss. Hence, the energy conservation law appears to be violated. The author reconsiders this circuit, and gives a complete explanation of it based on a new embedding of the switch model. The embedding consists of a family of smooth switches with a finite transition time, and therefore is much more general and more realistic than the standard model. Furthermore, the asymptotic analysis carried out not only shows that the switch accounts for the energy loss (and thus the energy conservation law is not violated), but also explains the mechanisms underlying the behaviour of the circuit. View full abstract»

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  • 10. Stray capacitance of a two-layer air-cored inductor

    Page(s): 565 - 572
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (725 KB)  

    A new analytic method for predicting the stray capacitance of a double layer coil with conducting shield and air core is presented. The method involves construction of a two-layer turn-to-turn circuit model, which includes the self-inductance and resistance of each turn, the mutual inductance representing the flux linkage between all turns, and the capacitance between adjacent turns and the capacitance between the outer turns and conducting shield. At high, low and zero frequency the model is reduced to an effective capacitance, inductance, and resistance respectively: for frequencies below the first self-resonant frequency the behaviour of the circuit is approximated by an RLC circuit. A new result is a recursive calculation of the stray capacitance of the high frequency circuit model. The method and stray capacitance value are compared to alternative models and stray capacitance predictions, and the limitations of the different approaches discussed. Comparisons with experimental measurements show good agreement at the fundamental self-resonance and confirm that the effect of a conducting shield is likely to be small for a closely-wound coil. View full abstract»

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  • 11. Design of an area-efficient CMOS multiple-valued current comparator circuit

    Page(s): 151 - 158
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1992 KB)  

    In the present state-of-the-art VLSI technology, the need for developing customised circuits to suit varying operating environments and specifications is escalating. The authors introduce an area-efficient current-mode comparator, which is based on modifications of the conventional CMOS current comparator. It has been verified by circuit simulations using the 0.25 μm, 0.18 μm, and 0.13 μm CMOS technology from Chartered Semiconductor Manufacturing Pte. Ltd (CHRT ) that the proposed design acts as a perfect complement to the conventional current comparator for low threshold current (Ith) levels. A low Ith is generally more favourable than a higher Ith as it tends to dissipate low static power. A more assuring and promising fact is that the area advantage becomes more significant with reducing feature size/technology. This attribute blends well with the contemporary and ongoing process technology miniaturisation. Together with the conventional and recently reported current comparator designs, the proposed current comparator has been integrated into a positive-digit adder (PDA) using the current-mode multiple-valued logic (CMMVL) approach with 1.8 V/0.18 μm CMOS technology. The PDA utilising the new current comparator occupies a silicon area of only 40.2 μm2, which is only 77.2% and 22.6% of those of the conventional and contemporary circuits, with a power-delay product improvement of 7.3% and 70.4%, respectively. View full abstract»

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  • 12. Approximation of sigmoid function and the derivative for hardware implementation of artificial neurons

    Page(s): 18 - 24
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (611 KB)  

    A piecewise linear recursive approximation scheme is applied to the computation of the sigmoid function and its derivative in artificial neurons with learning capability. The scheme provides high approximation accuracy with very low memory requirements. The recursive nature of this method allows for the control of the rate accuracy/computation-delay just by modifying one parameter with no impact on the occupied area. The error analysis shows an accuracy comparable to or better than other reported piecewise linear approximation schemes. No multiplier is needed for a digital implementation of the sigmoid generator and only one memory word is required to store the parameter that optimises the approximation. View full abstract»

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  • 13. CMOS differential difference current conveyors and their applications

    Page(s): 91 - 96
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    The authors present a new versatile circuit building block called a differential difference current conveyor (DDCC). An IC technique for implementing the DDCC is also presented. The DDCC-based frequency-selective circuits and nonlinear building blocks such as multiplier, squarer and square rooter are developed. Experimental results are given to demonstrate the feasibility of the proposed techniques, and they show that DDCC-based circuits offer a competitive design choice to CCII-based and DDA-based circuits View full abstract»

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  • 14. Design method for impedance matching networks

    Page(s): 186 - 194
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    The design of basic passive LC networks, with particular attention to the ubiquitous II network, is studied for conjugate matching any two impedances and meeting a specified loaded quality factor Q0. Algebraic design formulae are analytically demonstrated, which prove extremely simple. Explicit expressions of network frequency responses and harmonic rejection in terms of the loaded Q0 and the given impedances are established and a method for determining the loaded Q0 for any required harmonic attenuation is developed. The authors formulate and discuss all tolerance and parasitic sensitivities and their relation to the loaded Q0. The design method is also presented from the power transmission viewpoint. In particular, actual power transmission relations, taking the finite unloaded Qu into account, are derived in terms of the loaded and unloaded Q. The authors also address the design problem with regard to the standing wave ratio and reflection coefficient. Using the relations derived we can achieve both the maximum power transfer and the required harmonic rejection at any frequencies precisely, and we can also readily evaluate and incorporate other performances, View full abstract»

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  • 15. Active noise cancellation with a fuzzy adaptive filtered-X algorithm

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    The authors present a fuzzy adaptive filtered-X algorithm for active noise cancellation (ANC) in ducts, using fuzzy rules to construct an anti-noise filter to cancel out the undesired noise. Complex acoustic plant models, such as those used in conventional ANC systems, can be disregarded in the proposed fuzzy technique. As a new method for ANC, the proposed system tunes the free parameters automatically and changes the IF-THEN rules adaptively to minimise the residual noise as new information becomes available. Hence, the proposed algorithm can be easily constructed at the beginning, and the complexity of building an ANC system can be reduced. Direct numerical simulations demonstrate the effectiveness of the proposed design View full abstract»

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  • 16. Low voltage, low power, high performance current mirror for portable analogue and mixed mode applications

    Page(s): 273 - 278
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (607 KB)  

    A novel current mirror (CM), suitable for operation at low voltage levels is presented. The mirror has high input and high output voltage swings. Adaptive current biasing is introduced for minimising the effects of offset current. A compensation technique has been used to increase the bandwidth. This makes the CM structure attractive for portable, high frequency circuit applications. P-SPICE simulations, based on models for 1.2 μm technology, validate the operation of the proposed current mirror for currents from 1 to 500 μA with 1.2 GHz bandwidth View full abstract»

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  • 17. High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration

    Page(s): 308 - 314
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (989 KB)  

    A high-performance current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Simulation results have shown that the new sense amplifier gives performance leverage over the conventional sense amplifier circuits in terms of speed and power. View full abstract»

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  • 18. Linearity analysis and design optimisation for 0.18 μm CMOS RF mixer

    Page(s): 112 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    Equations for the 1dB compression point and third-order intermodulation point as a function of circuit and technology parameters are derived using a Volterra series expansion. The linearity analysis for both single- and double-balanced CMOS Gilbert mixers is examined. The relation between the input third-order intercept point and source inductance is studied in depth. The gate to drain overlap capacitance, which is one of the dominant nonlinear elements in a MOSFET, is included in the model. The design methodology to satisfy the mixer noise figure and conversion gain while optimising linearity is summarized. The analytical predictions are verified with the Cadence SpectreRF circuit simulation and experimental data. Good agreement between the model predictions and experimental data is obtained View full abstract»

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  • 19. Application of a CMOS current mode approach to on-chip current sensing in smart power circuits

    Page(s): 357 - 363
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1004 KB)  

    A novel accurate CMOS current sensing circuit for the protection of smart power MOS switches, using the current mode approach is proposed. It has the advantage of not requiring any passive components and it is based on a CMOS current mode building block presenting a wide frequency bandwidth as well as temperature insensitivity. Two current sensing cells are necessary to detect open load, short-circuit and overcurrent situations. Detection is achieved by monitoring a small portion of the power switch current provided by a single-cell transistor (SENSEFET). The performance of these functions is analysed by electrical PSPICE simulations and experimental results obtained from a silicon test chip View full abstract»

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  • 20. Piecewise linear approximation applied to nonlinear function of a neural network

    Page(s): 313 - 317
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses a simple digital gate design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. The comparison of this technique with two other sigmoidal approximation techniques for digital circuits is presented and the results show that the fast and compact digital circuit proposed produces the closest approximation to the sigmoid function, The hardware implementation of PLAN has been verified by a VHDL simulation with Mentor Graphics running under the UNIX operating system View full abstract»

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  • 21. High performance 5 : 2 compressor architectures

    Page(s): 447 - 452
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (383 KB)  

    Fast arithmetic circuits are key elements of high performance computers and data processing systems. In the majority of these applications, multipliers have been a critical and obligatory component in dictating the overall circuit performance when constrained by power consumption and computation speed. Compressors are a critical component of the multiplier circuit, which greatly influence the overall multiplier speed. The authors propose two novel high performance 5 : 2 compressor architectures. The main objective of their designs is to limit the carry propagation to a single stage, thereby reducing the overall propagation delay. The designs are compared with the best one in the literature in terms of delay and are found to have lower values. The analytical techniques use the node capacitances in the signal delay paths to identify the worst delay path. The architectures are implemented with various XOR-XNOR circuits to identify the best one in terms of power and delay. The simulation results of the proposed architectures show lower power and 25% improvement in speed compared to the best architecture reported in the literature for supply voltages ranging from 1.5 V to 3.3 V View full abstract»

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  • 24. Radiation-induced changes in thin film structures

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (542 KB)  

    Optical, electrical and structural properties of metal oxide thin films of tellurium dioxide (TeO2), indium oxide (In2O3) and silicon monoxide (SiO) and their mixtures were studied in terms of gamma radiation influence. These films were prepared using the thermal vacuum evaporation technique. 60Co and 137Cs sources were used to expose the samples to γ-radiation. It was found that the optical band gap values decreased with increasing radiation dose. The radiation induced changes in the electrical properties of these films. Devices with resistor-type structures and p-n junctions were studied. Irradiation resulted in the degradation of the device performance, e.g. current-voltage characteristics of these devices experienced significant alterations. It was observed that values of current were increased with increasing radiation dose. The response of these devices to radiation was found to be composition-dependent. Radiation-induced changes in the structure and surface morphology of In2O3/SiO films were examined by scanning electron microscopy and X-ray diffraction. The irradiation of these thin films with a dose of 8160 μSv led to a change in their phase from amorphous to partially crystallised View full abstract»

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  • 25. Single fully differential current conveyor biquad filters

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (290 KB)  

    The authors present two new filter biquads based on the recently introduced fully differential current conveyor (FDCCII). The biquads use a single FDCCII, two grounded resistors and two grounded capacitors, which are the minimum components necessary to realise a second-order filtering response (low-pass, high-pass, band-pass, band-reject, and all-pass). This is unlike biquads reported by El-Adawy et al. (2000), which employ more active and passive components. Simulation results are included, validating the theoretical analysis View full abstract»

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  • 26. Pseudo-chaotic PN-sequence generator circuits for spread spectrum communications

    Page(s): 543 - 550
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (641 KB)  

    Novel approaches to pseudo-noise (PN) sequence generation are presented and applied to spread spectrum communications. These approaches exploit the direct quantisation of chaotic maps, which results in fully digital implementations of pseudo-chaotic sequence generators. The robust digital implementation eliminates the variation tolerance and electronic noise problems common in analogue chaotic circuits. A cell based sequence generator architecture has been developed and implemented as a prototype integrated circuit. The architecture exhibits sensitive dependence on initial conditions and is capable of generating a new class of pseudo-chaotic sequences. The simulation and test results indicate that distinct sequences suitable for spread spectrum communication systems can be easily generated in a robust, scalable and programmable manner using the presented approach. View full abstract»

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  • 27. Pipeline direct digital frequency synthesiser using decomposition method

    Page(s): 141 - 144
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6 μm single-poly double-metal (SPDM) CMOS process and its core area is 0.95×1.1 mm2. The maximum operating frequency is 85 MHz. For a 10 MHz sinusoidal output, the phase noise is -114 dBc/Hz at an offset frequency of 10 kHz. The measured SNR is 60.77 dB and worst case spurious is -67.6 dBc. Its power dissipation is 80 mW at 80 MHz under the 5 V supply View full abstract»

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  • 28. Comparative study of different current mode sense amplifiers in submicron CMOS technology

    Page(s): 154 - 158
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A comparison of different current mode sense amplifiers using 0.25 μm CMOS technology is presented. The sense amplifiers under consideration are suitable for current sensing in SRAM and flash non-volatile memories. Simulation results are given regarding the sensing delay time for different power supply voltages Vdd and bit-line capacitance values. Comparative results are also provided for the energy dissipated per sensing operation, while worst-case and high temperature simulations are included, in order to expose limitations of the sensors in various operating conditions View full abstract»

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  • 29. Fast and energy-efficient Manchester carry-bypass adders

    Page(s): 497 - 502
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    A new modified Manchester carry chain (MCC) is presented. The objective is to reduce the carry propagation delay in the chain obtaining a layout-oriented architecture. The modification provides bypass (carry-skip) routes for the carry to propagate through quickly, avoiding long carry propagation paths that go through the entire carry chain. When realised using AMS 0.35 μm 2-poly 3-metal 3.3 V CMOS technology (CSD), a 32-bit adder designed as described here shows a computational delay of about 2.2 ns and an energy dissipation of only 27 pJ. This represents a significant improvement in terms of energy-delay product with respect to both conventional MCC adders and newer adder structures. View full abstract»

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  • 30. CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

    Page(s): 539 - 544
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (475 KB)  

    Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 mum CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm2 (approximately) View full abstract»

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  • 31. Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit

    Page(s): 347 - 355
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    Pipelined cellular array implementations of arithmetic circuits are usually adopted to obtain high throughput at reasonable cost. The circuit design style used to implement the array greatly influences both performance and cost. The designer has to move in a varied and complex scenario, since nowadays scores of logic styles are known among CMOS families. Static logic styles are easy to use and they allow low power consumption, while dynamic logic styles have some potential advantages. These circuits tend to be faster and, at least for the implementation of simple logic functions, they require fewer transistors. Often the choice of the circuit design style is done by means of qualitative analysis. Referring to the creation of a pipelined square-rooting circuit, both static and dynamic implementations are quantitatively compared for several operand wordlengths. Using 0.5 μm technology parameters, a pre-layout comparison is performed in terms of net transistor area, number of transistors, propagation delay and average power dissipation. Results indicate that DOMINO logic implementation shows the best area-time-power trade-off. Then a set of standard cells has been designed to layout the DOMINO logic array. Post-layout data shows that a 32-bit array designed in this way and realised using 0.5 μm 3.3 V CMOS process reaches a maximum throughput rate up to 175 MHz, requires a silicon area of 1.4×1.4 mm2 and dissipates 1.59 mW/MHz. The proposed RCA-based circuit reaches a throughput comparable to that of CLA-based square-rooting arrays, implemented using conventional static CMOS circuitry, thereby saving area and power View full abstract»

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  • 32. Thin film polycrystalline silicon solar cell on ceramics with a seeding layer formed via aluminium-induced crystallisation of amorphous silicon

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (349 KB)  

    Thin film polycrystalline silicon solar cells on foreign substrates are viewed as one of the most promising approaches to cost reduction in photovoltaics. To enhance the quality of the film, the use of 'seeding layers' prior to deposition of active material is being investigated. It has been shown that a phenomenon suitable to create such a seeding layer is the aluminium-induced crystallisation of amorphous silicon. Previous work mainly considered glass as the substrate of choice, thereby introducing limitations on the deposition temperature. Results concerning the application of such a technique to ceramic substrates (allowing the use of high-temperature CVD) are described. Also, the first reported results of a solar cell made in silicon deposited on these seeding layers are presented View full abstract»

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  • 33. Low-power single- and double-edge-triggered flip-flops for high-speed applications

    Page(s): 118 - 122
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (869 KB)  

    The paper presents new low-power flip-flops which are faster compared to previously proposed structures. The single-edge-triggered flip-flop, called the MHLFF (modified hybrid latch flip-flop), reduces the power dissipation of the HLFF (hybrid latch flip-flop) by avoiding unnecessary node transitions. To reduce the power consumption of the flip-flop further, the double-edge-triggered modified hybrid latch flip-flop (DMHLFF) is also proposed. The power consumption in the clock tree is reduced by halving the clock frequency of the MHLFF for the same throughput. In addition to the low power, the speed is higher while the area is not larger. The increase in the speed is achieved by lowering the number of the stack transistors in the discharge path. View full abstract»

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  • 34. Fully differential current-mode third-order Butterworth VHF Gm-C filter in 0.18 μlm CMOS

    Page(s): 552 - 558
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1727 KB)  

    The authors present a new fully differential current-mode third-order Butterworth very high frequency Gm-C filter using current-mode linear transformation (CMLT) techniques. The systematic design method and procedure are developed to realise CMLT Gm-C filters efficiently. A third-order Butterworth lowpass filter with 200 MHz cutoff frequency, embedded bandgap reference and bias circuit is implemented in a TSMC 0.18 mum 1P6M process. The total harmonic distortion of the proposed current-mode filter is -46.5 dB at 200 MHz with input signal 0.4 mA. Power dissipation is 16.77 mW under 1.8 V supply voltage. Its core area occupies 0.163times0.186 mm2 . Both post-layout simulation and experimental results confirm the theoretical analysis. The proposed circuits can be extended to high-order Chebychev and elliptic filters View full abstract»

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  • 35. Finite element modelling of thermal fatigue effects in IGBT modules

    Page(s): 95 - 100
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    The effects of progressive thermal fatigue of the solder layer interface on the thermal performance of power module packages have been investigated. Specifically, in the paper the analysis of an 800 A-1800 V IGBT module using finite element techniques is performed. The use of this technique for modelling fatigue effects is thus demonstrated, and a method for estimating the fatigue lifetime of soldered power modules based on the Coffin-Manson relation is also given. Assessed parameters in the three-dimensional model are the thermal resistance, heat flux distribution through the different layers and maximum die temperature. The critical crack length at which the thermal resistance significantly increases is determined from the two-dimensional model. The temperature excursion and shear strain of the solder layer are estimated from dynamic analysis. Finally, all achieved models are calibrated by comparison of predicted results with simple theory and direct temperature measurements View full abstract»

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  • 36. Input impedance and output impedance of feedback amplifiers

    Page(s): 195 - 201
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    A simple and precise method is given for calculating the input and output impedances of a feedback amplifier, directly from its loop gain. A useful approximation to the precise result is that the input or output impedance is equal to the source or load impedance for which loop gain would equal unity View full abstract»

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  • 37. Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

    Page(s): 709 - 717
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (233 KB)  

    An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned ttopology operating under idea switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4 Ω, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500 mW (27 dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in th microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used. View full abstract»

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  • 38. Phase noise contribution of the phase/frequency detector in a digital PLL frequency synthesiser

    Page(s): 1 - 5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (375 KB)  

    A theoretical basis for the figure of merit method used to quantify the phase noise plateau of a PLL frequency synthesiser is described. Analyses are developed both to calculate the in-band phase noise of a given synthesiser architecture and to predict the figure of merit from the phase/frequency detector parameters. A range of experimental results is provided to validate the theory. View full abstract»

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  • 39. Thin film silicon materials and solar cells grown by pulsed PECVD technique

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (349 KB)  

    Pulsed plasma enhanced chemical vapour deposition (PECVD) involves modulation of standard 13.56 MHz RF plasma in the kilohertz range. This allows an increase in the electron density during the 'ON' cycle, while in the 'OFF' cycle, neutralising the ions responsible for dust formation in the plasma. The authors report the development of state-of-the-art nanocrystalline Si (nc-Si:H) materials using a pulsed PECVD technique with 220 crystallite orientation, grain size of ∼200 Å, low O concentration and a minority carrier diffusion length Ld of ∼1.2 μm. The crucial effects of the p/i interface and the incubation layer have been investigated and an efficiency of ∼7.5% for a single junction nc-Si:H p-i-n device has been achieved for an i-layer thickness of 1.4 μm, using non-optimised textured substrates View full abstract»

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  • 40. Power-source element and its properties

    Page(s): 220 - 226
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    A power-source element is defined and its properties are studied. The power source describes the output characteristics of the loss-free resistor, as well as high quality rectifiers, some types of switched-mode convertors, and other loss-less two-ports. It is shown that controlled power sources are inherent in the large class of buffered power-conservative two-port networks. This approach has inspired some new realisations and applications of the loss-free resistor. A family of high frequency switched-mode convertors is shown to exhibit naturally power-source output characteristics View full abstract»

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  • 41. Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

    Page(s): 402 - 408
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate-drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations View full abstract»

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  • 42. Comments on "CMOS differential difference current conveyors and their applications"

    Page(s): 335 - 336
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    For original paper see ibid., vol. 143, no. 2, p. 91-96 (1996 ). Recently Chiu, Liu, Ivan and Chen introduced a new active building block called a differential difference current conveyor (DDCC) and demonstrated its application in realising squarer, square rooter and multiplier circuits, differential integrators, and voltage mode (VM) and current mode (CM) low-pass/band-pass (LP/BP) filters. CMOS integrable implementations for DDCC+ and DDCC- (two separate circuits) were also proposed. This comment extends the domain of application of the DDCC to the realisation of CM all grounded passive elements (AGPE) SRCOs, not discussed by Chiu et al. or anyone else so far. In particular, we show that, if instead of considering DDCC+ and DDCC- as separate units, we consider a single unit which we call a differential difference complementary current conveyor (DDCCC), then such a DDCCC turns out to be a versatile device to implement CM AGPE SRCOs View full abstract»

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  • 43. Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors

    Page(s): 415 - 421
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (395 KB)  

    This study discusses the composite effect of channel length and gate oxide thickness scaling, coupled with the effect of gate dielectric nitridation on the 1/f noise of minimum channel length NMOS transistors. These transistors have been taken from four advance CMOS technologies with dual gate oxide thickness. The result shows that the current noise spectral density SId of a thin gate oxide transistor increases by approximately 1.5 orders of magnitude when scaling from 350 nm to 130 nm. This increase is closely correlated to the changeover from thermal oxides to nitrided oxides from 250 nm and below. This work also investigates the effect of nitridation on thick gate oxide transistors and compares them to their architecturally equivalent thin gate oxide non-nitrided counterpart from 350 nm technology. The comparison reveals that nitridation has increased the SId of architecturally equivalent thick gate oxide transistors from 250 nm to 130 nm technologies by a maximum of 1.25 orders of magnitude. The experimental 1/f noise trends have been verified with simulations using the BSIM3v3 flicker noise model. View full abstract»

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  • 44. Improved neuron MOS-transistor structures for integrated neural network circuits

    Page(s): 25 - 34
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of summation, thereby simulating the function of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. Integrated circuits for neural network applications have also been designed, based on the neuron MOS transistors. These circuits include neuron CMOS inverters and A/D and D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures and circuits are implemented by using a standard 0.8 μm double-polysilicon CMOS technology. Attention was paid to saving the layout area and reducing power consumption View full abstract»

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  • 45. High-frequency two-input CMOS OTA for continuous-time filter applications

    Page(s): 13 - 18
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 μm CMOS process (MOSIS) are presented. A tuning circuit is also discussed View full abstract»

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  • 46. High frequency and high resolution capacitance measuring circuit for process tomography

    Page(s): 215 - 219
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A stray-immune AC capacitance measuring circuit has been developed for electrical capacitance tomography. For this application a high excitation frequency is essential to achieve high sensitivity and fast data collection rates, and also to reduce the effect of any conductive component in parallel with the measured capacitance. A high excitation frequency has been made possible by using some novel methods: (a) a high frequency digital signal generator; (b) parameter-optimised AC amplifiers and (c) a phase-sensitive demodulator utilising CMOS switches. With a 500 kHz excitation signal the circuit has good linearity and stability, and a resolution of 0.035 fF View full abstract»

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  • 47. CMOS single-input differential-output amplifier cells

    Page(s): 194 - 198
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    The paper addresses the design of CMOS amplifiers with inherent single-to-differential conversion for use in high-frequency applications. Design techniques for stabilising the operating point and providing substantial increase in gain and/or bandwidth performance are also discussed. Simulations on designs using a 0.8-μm technology are provided confirming the accuracy of the expected performance. View full abstract»

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  • 48. Advanced SPICE modelling of SiGe HBTs using VBIC model

    Page(s): 129 - 135
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (695 KB)  

    The vertical bipolar intercompany (VBIC) model has been applied to silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The model includes the improved Early effect, quasi-saturation, substrate parasitic, avalanche multiplication, and self-heating. Several device parameters have been extracted from SiGe HBTs and implemented in the VBIC model. A comparison is made with the SPICE Gummel-Poon model. The usefulness and accuracy of the VBIC model for SiGe HBTs are demonstrated by way of comparison of simulated and measured room temperature device data View full abstract»

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  • 49. Simple and accurate extraction methodology for RF MOSFET valid up to 20 GHz

    Page(s): 587 - 592
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (662 KB)  

    An accurate and simple parameter extraction technique for deep submicron MOSFETs using a conventional MOSFET model with three terminal resistances for the gate, source and drain, as well as a simple substrate coupling network and a non-reciprocal capacitor is proposed. This extraction technique utilises both Z and Y parameter analysis on the proposed small-signal equivalent circuit. RF simulation is carried out using the BSIM4 DC core model with the extracted extrinsic components. Analytical equations are derived for all the RF parameters and a linear regression technique is used to extract the parameters. Transcapacitance is utilised in the model to ensure charge conservation and good fitting of the Y21 and Y12 parameters. The extracted and optimised RF parameter values are in close agreement, which implies that little or no optimisation is required using this technique. Hence, this extraction methodology can be implemented easily for RF MOSFET modelling. Excellent agreement has been obtained between the simulated and measured results up to 20 GHz. View full abstract»

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  • 50. Digital optical microphone and digital transducer

    Page(s): 135 - 139
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    The design of a new digital microphone using an optical technique is described. An interdigital photoconductive detector is explained and a new optical scanner is designed for this microphone. The important parameters for developing a digital microphone are presented, followed by the required modifications to obtain a digital transducer for the measurement of very small angles, displacements or pressure View full abstract»

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