# IEEE Transactions on Electron Devices

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• ### A 1.1- $mu text{m}$ 33-Mpixel 240-fps 3-D-Stacked CMOS Image Sensor With Three-Stage Cyclic-Cyclic-SAR Analog-to-Digital Converters

Publication Year: 2017, Page(s):4992 - 5000
| | PDF (3709 KB) | HTML

In this paper, a 1.1-μm-pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the... View full abstract»

• ### The Trench Power MOSFET: Part I—History, Technology, and Prospects

Publication Year: 2017, Page(s):674 - 691
Cited by:  Papers (3)
| | PDF (4002 KB) | HTML

The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench... View full abstract»

• ### GaN-on-Si Power Technology: Devices and Applications

Publication Year: 2017, Page(s):779 - 795
Cited by:  Papers (17)
| | PDF (4964 KB) | HTML

In this paper, we present a comprehensive review and discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior per... View full abstract»

• ### Theoretical Performance Limit of the IGBT

Publication Year: 2017, Page(s):4184 - 4192
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In this paper, an analytical model of insulated gate bipolar transistor (IGBT) on-state voltage (VON) and turn-off loss (EOFF) is developed to find the optimum solution (minimum power loss) for a given application. With this model, it is found that IGBT on-state voltage is limited by the fact that holes can only flow from the anode to the cathode. The minimum on-state voltage for a Si IGBT with 11... View full abstract»

• ### The Trench Power MOSFET—Part II: Application Specific VDMOS, LDMOS, Packaging, and Reliability

Publication Year: 2017, Page(s):692 - 712
Cited by:  Papers (3)
| | PDF (5223 KB) | HTML

The technological development of application specific VDMOS and lateral trench power MOSFETs is described. Unlike general-purpose trench vertical DMOS, application specific trench DMOS comprise devices merged or optimized for a specific function or characteristic. Examples include the bidirectional lithium ion battery disconnect switch, the airbag squib driver with safety redundancy, the antilock ... View full abstract»

• ### 14-nm FinFET Technology for Analog and RF Applications

Publication Year: 2018, Page(s):31 - 37
| | PDF (1928 KB)

This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a ${F}_{t}/{F}_{text {max}}$ of 314/180 GHz and 285/140 GHz for ${N}$ View full abstract»

• ### Phase-Change Memory—Towards a Storage-Class Memory

Publication Year: 2017, Page(s):4374 - 4385
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Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a stor... View full abstract»

• ### IGBT History, State-of-the-Art, and Future Prospects

Publication Year: 2017, Page(s):741 - 752
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An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today's power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown. All these measures will result on the one hand in ongoing power density and efficiency increase as im... View full abstract»

• ### Double-Gate Tunnel FET With High-κ Gate Dielectric

Publication Year: 2007, Page(s):1725 - 1733
Cited by:  Papers (497)  |  Patents (12)
| | PDF (638 KB) | HTML

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0... View full abstract»

• ### Active-Matrix GaN Micro Light-Emitting Diode Display With Unprecedented Brightness

Publication Year: 2015, Page(s):1918 - 1925
Cited by:  Papers (18)  |  Patents (1)
| | PDF (1571 KB) | HTML

Displays based on microsized gallium nitride light-emitting diodes possess extraordinary brightness. It is demonstrated here both theoretically and experimentally that the layout of the n-contact in these devices is important for the best device performance. We highlight, in particular, the significance of a nonthermal increase of differential resistance upon multipixel operation. These findings u... View full abstract»

• ### Ultrathin-Barrier AlGaN/GaN Heterostructure: A Recess-Free Technology for Manufacturing High-Performance GaN-on-Si Power Devices

Publication Year: 2018, Page(s):207 - 214
| | PDF (2711 KB)

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth an... View full abstract»

• ### Gate Leakage Mechanisms in AlInN/GaN and AlGaN/GaN MIS-HEMTs and Its Modeling

Publication Year: 2017, Page(s):3609 - 3615
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Gate leakage mechanisms in AlInN/GaN and AlGaN/GaN metal insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric have been investigated. It is found that the conduction in the reverse gate bias is due to Poole-Frenkel emission for both MIS-HEMTs. The dominant conduction mechanism in low to medium forward bias is trap-assisted tunneling while i... View full abstract»

• ### Electronic Conduction Mechanisms in Insulators

Publication Year: 2018, Page(s):223 - 230
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The current density–electric field ${(}{J}-xi {)}$ characteristics of four insulators of dramatically different electrical qualities are assessed in terms of their operative electronic conduction mechanisms. Conduction in the two high-quality insulators is dominated by Ohmic conduction and Fowler–Nordheim tunnel... View full abstract»

• ### Review on Thermionic Energy Converters

Publication Year: 2016, Page(s):2231 - 2241
Cited by:  Papers (7)
| | PDF (1888 KB) | HTML

Thermionic energy converter (TEC) is a heat engine that generates electricity directly using heat as its source of energy and electron as its working fluid. Despite having a huge potential as an efficient direct energy conversion device, the progress in vacuum-based thermionic energy converter development has always been hindered by the space charge problem and the unavailability of materials with... View full abstract»

• ### Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation

Publication Year: 2007, Page(s):3393 - 3399
Cited by:  Papers (329)  |  Patents (20)
| | PDF (880 KB) | HTML

We have developed a normally-off GaN-based transistor using conductivity modulation, which we call a gate injection transistor (GIT). This new device principle utilizes hole-injection from the p-AlGaN to the AlGaN/GaN heterojunction, which simultaneously increases the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation. The fa... View full abstract»

• ### A Review of Flexible OLEDs Toward Highly Durable Unusual Displays

Publication Year: 2017, Page(s):1922 - 1931
Cited by:  Papers (1)
| | PDF (3089 KB) | HTML

Organic light-emitting diodes (OLEDs) are remarkably promising display devices that can function in mechanically flexible configurations on a plastic substrate due to various compelling properties, including organic constituents, ultrathin and simple structure, and low-temperature fabrication. In spite of successful demonstrations of flexible OLEDs, some technical issues of containing relatively t... View full abstract»

• ### Impact of Substrate Bias Polarity on Buffer-Related Current Collapse in AlGaN/GaN-on-Si Power Devices

Publication Year: 2017, Page(s):5048 - 5056
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Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been inves... View full abstract»

• ### FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Publication Year: 2000, Page(s):2320 - 2325
Cited by:  Papers (757)  |  Patents (230)
| | PDF (136 KB)

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si0.4Ge0.6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated re... View full abstract»

• ### Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Publication Year: 2013, Page(s):3663 - 3668
Cited by:  Papers (2)
| | PDF (1025 KB) | HTML

This paper measures the n- and p-MOSFETs fabricated through 65-nm high- k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel c... View full abstract»

• ### 3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

Publication Year: 2017, Page(s):312 - 318
Cited by:  Papers (10)
| | PDF (3358 KB) | HTML

We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2-x/TiN/Pt memristors and consists of a stack of two passive 10 × 10 crossbars with shared middle electrodes. The fabrication process has a low, less th... View full abstract»

• ### Transconductance Amplification by the Negative Capacitance in Ferroelectric-Gated P3HT Thin-Film Transistor

Publication Year: 2017, Page(s):4974 - 4979
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With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor c... View full abstract»

• ### Neuromorphic Learning and Recognition With One-Transistor-One-Resistor Synapses and Bistable Metal Oxide RRAM

Publication Year: 2016, Page(s):1508 - 1515
Cited by:  Papers (13)
| | PDF (3941 KB) | HTML

Resistive switching memory (RRAM) has been proposed as an artificial synapse in neuromorphic circuits due to its tunable resistance, low power operation, and scalability. For the development of high-density neuromorphic circuits, it is essential to validate the state-of-the-art bistable RRAM and to introduce small-area building blocks serving as artificial synapses. This paper introduces a new syn... View full abstract»

• ### Temperature and Bias Dependent Trap Capture Cross Section in AlGaN/GaN HEMT on 6-in Silicon With Carbon-Doped Buffer

Publication Year: 2017, Page(s):4868 - 4874
| | PDF (1898 KB) | HTML

We report on the estimation of trap capture cross section in AlGaN/GaN HEMTs as a function of bias and temperature. Conductance dispersion technique was employed to study the AlGaN/GaN interface of the devices with a carbon-doped GaN buffer grown on 6-in silicon. While a negligible shift in the threshold voltage (VTH) was observed in temperature-dependent IDS-VGS sweeps, we observed a spread in th... View full abstract»

• ### Schottky Tunneling Effects in a Tunnel FET

Publication Year: 2017, Page(s):5223 - 5229
| | PDF (3798 KB) | HTML

Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to replace IM-FETs. As the channel length is short... View full abstract»

• ### Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

Publication Year: 2017, Page(s):4071 - 4077
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State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-... View full abstract»

• ### SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Schottky Barrier Diode

Publication Year: 2018, Page(s):347 - 351
| | PDF (2208 KB)

A silicon carbide (SiC) trench MOSFET (TMOS) with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation. The device features the integrated TLP-SBD that remarkably improves body diode characteristics while guarantees excellent fundamental performance of TMOS. In the blocking state, the P-base region, the trench gate, and th... View full abstract»

• ### A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path

Publication Year: 2017, Page(s):4910 - 4918
| | PDF (4084 KB) | HTML

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n... View full abstract»

• ### The impact of surface states on the DC and RF characteristics of AlGaN/GaN HFETs

Publication Year: 2001, Page(s):560 - 566
Cited by:  Papers (723)  |  Patents (4)
| | PDF (136 KB) | HTML

GaN based HFETs are of tremendous interest in applications requiring high power at microwave frequencies. Although excellent current-voltage (I-V) characteristics and record high output power densities at microwave frequencies have been achieved, the origin of the 2DEG and the factors limiting the output power and reliability of the devices under high power operation remain uncertain. Drain curren... View full abstract»

• ### Investigation of Self-Heating Effects in Gate-All-Around MOSFETs With Vertically Stacked Multiple Silicon Nanowire Channels

Publication Year: 2017, Page(s):4393 - 4399
| | PDF (2222 KB) | HTML

The self-heating effects (SHEs) in gate-all-around (GAA) MOSFETs with vertically stacked silicon nanowire (SiNW) channels are investigated. Direct observations using thermal images, electrical proof measurements, and supportive numerical simulations are carried out to verify the SHEs. This paper examines the location of hot spots as well as heat dissipation paths (heat sink) depending on the devic... View full abstract»

• ### Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Publication Year: 2017, Page(s):5284 - 5287
| | PDF (1111 KB) | HTML

The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of ... View full abstract»

• ### Resistive Switching Device Technology Based on Silicon Oxide for Improved ON–OFF Ratio—Part II: Select Devices

Publication Year: 2018, Page(s):122 - 128
| | PDF (2444 KB)

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop sc... View full abstract»

• ### Analytical Model for the Threshold Voltage of ${p}$ -(Al)GaN High-Electron-Mobility Transistors

Publication Year: 2018, Page(s):79 - 86
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An analytical model for the calculation of the threshold voltage for enhancement-mode (E-mode) ${p}$ -(Al)GaN high-electron-mobility transistors (HEMTs) is presented. The ON-state behavior (at low output voltages) of both ${p}$ -GaN HEMTs and View full abstract»

• ### Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications

Publication Year: 2013, Page(s):2982 - 2996
Cited by:  Papers (118)  |  Patents (3)
| | PDF (9192 KB) | HTML

In this paper, we report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures, a low-resistance n+-GaN/2DEG ohmic contact regrown by MBE... View full abstract»

• ### Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Publication Year: 2017, Page(s):2707 - 2713
| | PDF (4697 KB) | HTML

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc ... View full abstract»

• ### Superjunction Power Devices, History, Development, and Future Prospects

Publication Year: 2017, Page(s):720 - 734
Cited by:  Papers (3)
| | PDF (4268 KB) | HTML

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and proces... View full abstract»

• ### Considerations for Ultimate CMOS Scaling

Publication Year: 2012, Page(s):1813 - 1828
Cited by:  Papers (218)  |  Patents (4)
| | PDF (1217 KB) | HTML

This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared b... View full abstract»

• ### The Role of Silicon Substrate on the Leakage Current Through GaN-on-Si Epitaxial Layers

Publication Year: 2018, Page(s):51 - 58
| | PDF (2331 KB)

We present an investigation of vertical leakage in GaN-on-Si epitaxial stack through electrical characterization and device simulations. Different structures of increasing complexity have been fabricated and analyzed in order to achieve a complete understanding of the main transport mechanisms. We have clarified the role of the Si substrate through comparison of identical structures built on p-typ... View full abstract»

• ### Current Status and Opportunities of Organic Thin-Film Transistor Technologies

Publication Year: 2017, Page(s):1906 - 1921
Cited by:  Papers (3)
| | PDF (3448 KB) | HTML

Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic funct... View full abstract»

• ### Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Publication Year: 2018, Page(s):11 - 18
| | PDF (2040 KB)

Transconductance efficiency ( ${g}_{m}/{I}_{D}$ ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of ${g}_{m}/{I}_{D}$ versus normalized drain current curve is analyzed in an asymmetric double-g... View full abstract»

• ### Characterization, Modeling, and Application of 10-kV SiC MOSFET

Publication Year: 2008, Page(s):1798 - 1806
Cited by:  Papers (133)  |  Patents (1)
| | PDF (738 KB) | HTML

Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losse... View full abstract»

• ### Effect of Source–Drain Doping on Subthreshold Characteristics of Short-Channel DG MOSFETs

Publication Year: 2017, Page(s):4856 - 4860
| | PDF (1434 KB) | HTML

The effect of source-drain (S-D) doping on short-channel effects (SCEs) of double-gate MOSFETs is investigated by analytically solving the 2-D potential function in subthreshold. The depleted bands of the degenerately doped S-D regions are coupled to the channel bands through continuity of the electric field at the junction. Both the conduction band profile and the subthreshold Ids-Vg characterist... View full abstract»

• ### Comparative Study of Negative Capacitance Ge pFETs With HfZrOx Partially and Fully Covering Gate Region

Publication Year: 2017, Page(s):4838 - 4843
| | PDF (3065 KB) | HTML

We report a comparative study of the negative capacitance (NC) Ge pFETs with HfZrOx (HZO) partially and fully covering gate region. Utilizing the layout with HZO partially covering the gate, the internal voltage gain dVint/dVGS > 10 is demonstrated in NC Ge pFETs, which is attributed to the NC effect induced by HZO film. NC transistor demonstrates the hysteresis... View full abstract»

• ### Optimization of Au-Free Ohmic Contact Based on the Gate-First Double-Metal AlGaN/GaN MIS-HEMTs and SBDs Process

Publication Year: 2018, Page(s):622 - 628
| | PDF (3583 KB)

The compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts in the gate-first double-metal (GFDM) process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and Schottky barrier diodes (SBDs) on the same 150-mm wafer was investigated and discussed for the first time, including contact pretreatments, Al diffusion in dielectric layers, and vias (contact windows... View full abstract»

• ### Approaching the Quantum Limit of Photodetection in Solid-State Photodetectors

Publication Year: 2017, Page(s):4812 - 4822
| | PDF (1978 KB) | HTML

Many aspects of life involve sensitive photodetection, which is now widely implemented in solid-state devices made from semiconductor materials due to their relatively low cost, high scalability, and better compatibility with the existing CMOS technology. State-of-the-art Geiger-mode avalanche detectors and the challenges they faced in single-photon detection efficiency and timing resolution are c... View full abstract»

• ### Graphene Field-Effect Transistor Model With Improved Carrier Mobility Analysis

Publication Year: 2015, Page(s):3433 - 3440
Cited by:  Papers (7)
| | PDF (3611 KB) | HTML

This paper presents a SPICE-like graphene field-effect transistor (GFET) model with an improved carrier mobility analysis. The model considers the mobility difference between the electrons and the holes in graphene, as well as the mobility variation against the carrier density. Closed-form analytical solutions have been derived, and the model has been implemented in Verilog-A language. This was co... View full abstract»

• ### Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi-Saturation

Publication Year: 2018, Page(s):199 - 206
| | PDF (3696 KB)

Various LDMOS device design parameters to mitigate quasi-saturation (QS) have been identified. Based on this, a set of independent and mixed device designs to mitigate QS, while maximizing the device performance, are presented. The impact of QS on the analog/RF/switching performance of these independent and mixed designs is investigated thoroughly, while analogizing performance with QS for the fir... View full abstract»

• ### An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation

Publication Year: 2011, Page(s):2729 - 2737
Cited by:  Papers (202)  |  Patents (2)
| | PDF (1029 KB) | HTML

The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. TiN/HfOx/AlOx/ Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decr... View full abstract»

• ### Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM—Part II: Modeling

Publication Year: 2012, Page(s):2468 - 2475
Cited by:  Papers (176)  |  Patents (1)
| | PDF (1398 KB) | HTML

Resistive-switching memory (RRAM) based on transition metal oxides is a potential candidate for replacing Flash and dynamic random access memory in future generation nodes. Although very promising from the standpoints of scalability and technology, RRAM still has severe drawbacks in terms of understanding and modeling of the resistive-switching mechanism. This paper addresses the modeling of resis... View full abstract»

• ### Demonstration of Constant 8 W/mm Power Density at 10, 30, and 94 GHz in State-of-the-Art Millimeter-Wave N-Polar GaN MISHEMTs

Publication Year: 2018, Page(s):45 - 50
| | PDF (1371 KB)

This paper reports on state-of-the-art millimeter-wave power performance of N-polar GaN-based metal–insulator–semiconductor high-electron-mobility transistors at 30 and 94 GHz. The performance is enabled by our N-polar deep recess structure, whereby a GaN cap layer is added in the access regions of the transistor to simultaneously enhance the access region conductivity while mitigati... View full abstract»

• ### Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET

Publication Year: 2018, Page(s):3 - 10
| | PDF (2113 KB)

In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages. The structure is based upon asymmetric gate oxide structure by combining silicon ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy