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Solid-State Circuits, IEEE Journal of

Top Documents Accessed: Dec 2009

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1.	A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC Devarajan, S.; Singer, L.; Kelly, D.; Decker, S.; Kamath, A.; Wilkins, P. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3305-3313 Digital Object Identifier 10.1109/JSSC.2009.2032636 Summary: A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to...

	Abstract \| Full Text: PDF (1512 KB)

2.	A 10-Bit 500-MS/s 55-mW CMOS ADC Verma, A.; Razavi, B. Solid-State Circuits, IEEE Journal of Volume 44, Issue 11, Date: Nov. 2009, Pages: 3039-3050 Digital Object Identifier 10.1109/JSSC.2009.2031044 Summary: A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and d...

	Abstract \| Full Text: PDF (1291 KB)

3.	A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ Xiang Gao; Klumperink, E.A.M.; Bohsali, M.; Nauta, B. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3253-3263 Digital Object Identifier 10.1109/JSSC.2009.2032723 Summary: This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied b...

	Abstract \| Full Text: PDF (1183 KB)

4.	A 1 MHz Bandwidth, 6 GHz 0.18 $\mu$ m CMOS Type-I $\Delta \Sigma$ Fractional-N Synthesizer for WiMAX Applications Hedayati, H.; Khalil, W.; Bakkaloglu, B. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3244-3252 Digital Object Identifier 10.1109/JSSC.2009.2032713 Summary: A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization ...

	Abstract \| Full Text: PDF (1500 KB)

5.	A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry Marcu, C.; Chowdhury, D.; Thakkar, C.; Jung-Dong Park; Ling-Kai Kong; Tabesh, M.; Yanjie Wang; Afshar, B.; Gupta, A.; Arbabian, A.; Gambini, S.; Zamani, R.; Alon, E.; Niknejad, A.M. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3434-3447 Digital Object Identifier 10.1109/JSSC.2009.2032584 Summary: This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all ...

	Abstract \| Full Text: PDF (2587 KB)

6.	A 2.4-GHz Resistive Feedback LNA in 0.13- $\mu$ m CMOS Sanghoon Joo; Tae-Young Choi; Byunghoo Jung Solid-State Circuits, IEEE Journal of Volume 44, Issue 11, Date: Nov. 2009, Pages: 3019-3029 Digital Object Identifier 10.1109/JSSC.2009.2031912 Summary: A g_m-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback to...

	Abstract \| Full Text: PDF (1749 KB)

7.	A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz $1/f$ Noise Corner and an AC-Coupled Ripple Reduction Loop Rong Wu; Makinwa, K.A.A.; Huijsing, J.H. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3232-3243 Digital Object Identifier 10.1109/JSSC.2009.2032710 Summary: This paper presents a chopper instrumentation amplifier for interfacing precision thermistor bridges. For high CMRR and DC gain, the amplifier employs a three-stage current-feedback topology with nested-Miller compensation. By chopping both the input ...

	Abstract \| Full Text: PDF (1700 KB)

8.	A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta \Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS Park, M.; Perrott, M.H. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3344-3358 Digital Object Identifier 10.1109/JSSC.2009.2032703 Summary: The use of a VCO-based integrator and quantizer within a continuous-time (CT) ¿¿ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 ¿m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz ba...

	Abstract \| Full Text: PDF (3281 KB)

9.	A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction Panigada, A.; Galton, I. Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3314-3328 Digital Object Identifier 10.1109/JSSC.2009.2032637 Summary: This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity and DAC noise cancellation (DNC) to compensat...

	Abstract \| Full Text: PDF (2237 KB)

10.	A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC Brooks, L.; Hae-Seung Lee Solid-State Circuits, IEEE Journal of Volume 44, Issue 12, Date: Dec. 2009, Pages: 3329-3343 Digital Object Identifier 10.1109/JSSC.2009.2032639 Summary: Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of p...

	Abstract \| Full Text: PDF (1580 KB)

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