By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 11 • Date Nov 1995

Filter Results

Displaying Results 1 - 11 of 11
  • Test set compaction for combinational circuits

    Publication Year: 1995, Page(s):1370 - 1378
    Cited by:  Papers (46)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation for cyclic combinational circuits

    Publication Year: 1995, Page(s):1408 - 1414
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    Circuits that have an underlying acyclic topology are guaranteed to be combinational since feedback is necessary for sequential behavior. However, the reverse is not true, i,e., feedback is not a sufficient condition since there do exist combinational logic circuits that are cyclic. In fact, such combinational circuits occur often in bus structures in data paths. This class of circuits has largely... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • LILA: layout generation for iterative logic arrays

    Publication Year: 1995, Page(s):1359 - 1369
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented. Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data paths in microprocessors) is still mainly performed manually, and is a major bottleneck of the design. In L... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations

    Publication Year: 1995, Page(s):1402 - 1407
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    We present a strongly code disjoint (SCD) built-in current sensor (BICS) based on self-exercising concept. The integration of this SCD BICS with a self-checking circuit achieves the totally self-checking goal in static CMOS realizations, even in the presence of stuck-on and bridging faults, and results in a strongly fault-secure realization. Low-cost and high fault coverage is attractive for many ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiway partitioning via geometric embeddings, orderings, and dynamic programming

    Publication Year: 1995, Page(s):1342 - 1358
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1484 KB)

    This paper presents effective algorithms for multiway partitioning. Confirming ideas originally due to Hall (1970), we demonstrate that geometric embeddings of the circuit netlist can lead to high-quality k-way partitionings. The netlist embeddings are derived via the computation of d eigenvectors of the Laplacian for a graph representation of the netlist. As Hall did not specify how to partition ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Discretization of flux densities in device simulations using optimum artificial diffusivity

    Publication Year: 1995, Page(s):1309 - 1315
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The discretization scheme for the current density and the energy flux density has been revisited from a numerical diffusion point of view. A general discretization scheme for both flux densities is provided using the optimum artificial diffusivity. This formulation is equivalent to that of Scharfetter and Gummel in most cases but is numerically more transparent. It has the advantage that one formu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in self test for C-testable ILA's

    Publication Year: 1995, Page(s):1388 - 1398
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On squashing hierarchical designs [VLSI]

    Publication Year: 1995, Page(s):1398 - 1402
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    The problem of partially expanding a hierarchical VLSI design is examined, with the goal of reducing the number of levels of hierarchy while incurring minimal design-size expansion. While the general problem appears NP-hard, an important special case is considered, where the number of levels of hierarchy is reduced by one. For this special case, an exact algorithm is developed, based on network-fl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of combinational logic circuits based on compatible gates

    Publication Year: 1995, Page(s):1316 - 1327
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    This paper presents a set of new techniques for the optimization of multiple-level combinational Boolean networks. We describe first a technique based upon the selection of appropriate multiple-output subnetworks (consisting of so-called compatible gates) whose local functions can be optimized simultaneously. We then generalize the method to optimize larger and more arbitrary subsets of gates, cal... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Shrinking wide compressors [BIST]

    Publication Year: 1995, Page(s):1379 - 1387
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISR's) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISR's that may include several hundred stages. Wide MISR's pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, nee... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient calculation of spectral coefficients and their applications

    Publication Year: 1995, Page(s):1328 - 1341
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1148 KB)

    Spectral methods for analysis and design of digital logic circuits have been proposed and developed for several years. The widespread use of these techniques has suffered due to the associated computational complexity. This paper presents a new approach for the computation of spectral coefficients with polynomial complexity. Usually, the computation of the spectral coefficients involves the evalua... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu