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Computers and Digital Techniques, IEE Proceedings -

Issue 5 • Date Sep 1995

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Displaying Results 1 - 12 of 12
  • Enhancing the security of El Gamal's signature scheme

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (48 KB)  

    J. He and T. Kiesler (1994) proposed a digital signature scheme to embed both the discrete logarithm problem and the factorisation problem in the processing of signing to enhance the security of the original El Gamal signature scheme (1985). The purpose of this comment is to show that the security of the signature scheme is not as secure as they have claimed View full abstract»

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  • Cheating detection and cheater identification in secret sharing schemes

    Page(s): 367 - 369
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    A threshold scheme for secret sharing can protect a secret with high reliability and flexibility. These advantages can be achieved only when all the participants are honest, i.e. all the participants willing to pool their shadows shall always present the true ones. Cheating detection is an important issue in the secret sharing scheme. However, cheater identification is more effective than cheating detection in realistic applications. If some dishonest participants exist, the other honest participants will obtain a false secret, while the cheaters may individually obtain the true one. The paper presents a method to enforce the security of any threshold scheme with the ability to detect cheating and identify cheaters. By applying a one-way hashing function along with the use of arithmetic coding, the proposed method can be used to deterministically detect cheating and identify the cheaters, no matter how many cheaters are involved in the secret reconstruction View full abstract»

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  • Recursive relationships, fast transforms, generalisations and VLSI iterative architecture for Gray code ordered Walsh functions

    Page(s): 325 - 331
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Two Walsh transforms in Gray code ordering are introduced. The generation of two Walsh transforms in Gray code ordering from the binary code is shown. Recursive relationship between higher and lower matrix orders for Gray code ordering of Walsh functions, using the concepts of operator matrices with symmetric and shift copy, are developed. The generalisation of the introduced Gray code ordered Walsh functions for arbitrary polarity is shown. Another recursive algorithm for a fast Gray code ordered Walsh transform, which is based on the new operators on matrices, joint transformations and a bisymmetrical pseudo-Kronecker product, is introduced. The latter recursive algorithm is the basis for the implementation of a constant-geometry iterative architecture for the Gray code ordered Walsh transform. This architecture can be looped n times or cascaded n times to produce a useful VLSI integrated circuit View full abstract»

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  • The security of He and Kiesler's signature schemes

    Page(s): 370 - 372
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    He and Kiesler (1994) proposed two modified schemes to enhance the security of El Gamal's signature scheme (1985). They claimed to have remedied two technical problems of El Gamal's signature scheme, and the security of the second scheme is based on the difficulty of solving both factoring and discrete logarithms simultaneously. The paper shows that both modified schemes, in fact, do not solve the first technical problem. Besides, if one has the ability to solve the discrete logarithms, one can break the second modified signature scheme View full abstract»

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  • On the Matsumoto and Imai human identification scheme

    Page(s): 313 - 317
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    At Eurocrypt'91, Matsumoto and Imai presented a human identification scheme suitable for the human ability of memorising and processing a short secret. It protects against an intruder peeping as a user enters authentication information on a terminal connected to the authentication server. In this paper several attacks are discussed to investigate the security of their scheme. A modified scheme is proposed to avoid these attacks View full abstract»

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  • Reliability of semiconductor RAMs with soft-error scrubbing techniques

    Page(s): 337 - 344
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    Error control codes are widely used to improve the reliability of random-access memory (RAM) systems. The paper evaluates the reliability of coded memory systems suffering both hard (permanent) errors and soft (transient) errors. The technique of soft error scrubbing, that is periodically removing all soft errors to improve the system reliability, is studied for RAM systems with chip-level coding only (one-level fault tolerance) and both board-level and chip-level codings (two-level fault tolerance). Previous work, which covers hard errors only, is extended to include the technique of soft-error scrubbing. In addition, the assumption that the error rates among the different memory components are the same is removed. The result offers a simple and low-computational way of estimating the reliability of semiconductor RAMs protected by the error control codes View full abstract»

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  • Two parallel paths in incomplete hypercubes

    Page(s): 353 - 359
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    Previous routeing algorithms for incomplete hypercubes deal only with single-path routeing and fail to take advantage of the flexibility provided by incomplete hypercubes. The authors present a simple effective routeing algorithm that forwards messages through two parallel paths between a pair of nodes in any incomplete hypercube with an even number of nodes. This algorithm proves to be deadlock-free under both store-and-forward and wormhole routeing modes. The mean latency for sending large size messages is apparently reduced by forwarding them to their destinations through two parallel paths. This reduction in latency would result in a significant performance improvement. This algorithm can also tolerate one fault in the system by sending duplicate copies of messages through two parallel paths View full abstract»

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  • Weighted BIST structures in the arithmetic unit of a communication processor

    Page(s): 360 - 366
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    BIST structures using CAR and LFSR have shown important progress in the last few years as ASIC design styles have changed from (purely small) flattened standard cells to large hierarchical designs based on multiple module types: ALUs, RAMs, ROMs etc. The weighted self/test reduces the length of test experiments and gives an improvement in the BIST operation if it is possible to implement a weighted random test vector generation with a low area overhead in the circuit under test. These structures need to be flexible enough to be adapted to the different circuit modules. The authors propose a new circuit structure to generate a random test vector with weighted probability using LFSR or CAR multiple chains with a simple concatenation. The application of these BIST structures to the design of a communication processor with self test demonstrates the capacity for improvement in the test phase in these circuits. The authors present the results of the BIST structures designed with weighted self test and the design of the arithmetic unit with a weighted self test BIST on a communication processor View full abstract»

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  • Non-exhaustive method for identification of optimal variable orderings in the decomposition of complex logic functions

    Page(s): 373 - 375
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    An analysis is presented to predict the input variable subsets that give efficient disjunctive decompositions of complex combinatorial logic functions. A substantially smaller number of possible solutions, compared to all possible solutions, is predicted using a comparatively simple analysis, based on a count of the covers between tuples in the function description when one or two variables are swapped across the input variable partition. From these data, prominent variables, whose positions heavily influence the function decomposition, can be predicted and optimal orderings obtained. The effectiveness and efficiency of the method is demonstrated through a number of examples View full abstract»

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  • Lower bound study on interconnect complexity of the decomposed finite state machines

    Page(s): 332 - 336
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    Various strategies for multiway general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic level implementation. In the paper the authors are concerned with the lower bound on the number of interconnecting wires that must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view, having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multiway decomposition of an arbitrary machine, and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are highly decomposable from an interconnect point of view View full abstract»

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  • Techniques for ASIC implementation of vector control

    Page(s): 318 - 324
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Harmonic-free vector control, in which both the phase and amplitude of a three-phase current are controlled digitally to within close limits, is a common requirement in many power conversion applications. These include the control of three-phase motors, and the conversion of electrical power from three-phase AC to DC, or the inverse, with low supply harmonic content. Vector control at a specified frequency relies upon the generation of accurate sine and cosine waves, computation of the in-phase and quadrature components of the input current, and then reconversion to the three-phase sinusoidally varying drive values. The authors discuss the options available for implementation of the reference sine generator as an ASIC cell, and show how an application specific processor can be designed to achieve the very high performance combined with small area necessary to deal with the current transformation. Both functions are integrated in a design using less than 25000 gate equivalents at 16-bit accuracy View full abstract»

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  • Efficient computation of quaternary fixed polarity Reed-Muller expansions

    Page(s): 345 - 352
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    A new fast algorithm for constructing the whole polarity coefficient matrices of fixed polarity Reed-Muller expansions over Galois Field GF(4) has been introduced. The matrices are generated in a recursive way making the algorithm computationally very effective in terms of basic field operations. The number of required additions and multiplications is advantageous when compared to the known Green's algorithms. It is also possible to generate fixed polarity quaternary Reed-Muller expansion in some chosen polarity without the necessity of going through all the steps and recursions of the full algorithm. Fast flow diagrams for implementation of the new algorithms in hardware have also been shown View full abstract»

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