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IEEE Transactions on Computers

Issue 10 • Oct 1995

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Displaying Results 1 - 11 of 11
  • Measuring cache and TLB performance and their effect on benchmark runtimes

    Publication Year: 1995, Page(s):1223 - 1235
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1296 KB)

    In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (1) developing a high level program to measure the design and performance of the cache and TLB units; (2) using those measurements, along with published miss ratio ... View full abstract»

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  • Refinable bounds for large Markov chains

    Publication Year: 1995, Page(s):1216 - 1222
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A method to bound the steady-state solution of large Markov chains is presented. It integrates the concepts of eigen-vector polyhedron and of aggregation and is iterative in nature. The bounds are obtained by considering a subset only of the system state space. This makes the method specially attractive for problems which are too large to be dealt with by traditional methods. The quality of the bo... View full abstract»

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  • The performance of crossbar-based binary hypercubes

    Publication Year: 1995, Page(s):1208 - 1215
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Wormhole routing is an attractive routing technique offering low latency communication without the need to buffer an entire packet in a single node. A new queueing-theoretic model for obtaining throughput and latency of binary hypercubes supporting wormhole routing is developed here. The model is very accurate in predicting the performance of an actual multicomputer over a range of network sizes, ... View full abstract»

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  • Characterizing the performance of algorithms for lock-free objects

    Publication Year: 1995, Page(s):1194 - 1207
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1244 KB)

    Concurrent access to shared data objects must be regulated by a concurrency control protocol to ensure correctness. Many concurrency control protocols require that a process set a lock on the data it accesses. Recently, there has been considerable interest in lock-free concurrency control algorithms. Lock-free algorithms offer the potential for better system performance because slow or failed proc... View full abstract»

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  • Valved routing: efficient flow control for adaptive nonminimal routing in interconnection networks

    Publication Year: 1995, Page(s):1181 - 1193
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    Adaptive nonminimal routing (or misrouting) may move messages away from their destinations to temporarily cope with the dynamic load in an interconnection network. In most cases, misrouting is more powerful and flexible than minimal routing, especially under nonuniform load distribution. However, to take advantage of its misrouting, we have to avoid deadlock, livelock, and starvation in the networ... View full abstract»

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  • Broadcast ring sandwich networks

    Publication Year: 1995, Page(s):1169 - 1180
    Cited by:  Papers (34)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    In this paper we present a constructive design of a new class of cascaded network structures for broadcast applications called ring sandwich networks. These ring sandwich networks are rearrangeable in the sense that a request for a connection between a sender and a receiver can sometimes be realized only by first rearranging other existing connection paths through the network. We present analytica... View full abstract»

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  • A low-cost high-capacity associative memory design using cellular automata

    Publication Year: 1995, Page(s):1260 - 1264
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The present paper reports a novel scheme for designing fast retrieval memory system using cellular automata. In essence, the proposed scheme implements the concept of hashing in hardware. This makes possible the design of low-cost high-capacity memory systems with limited content addressability as an option. The efficiency of the scheme has been verified through extensive simulation studies of the... View full abstract»

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  • Design and performance analysis of a disk array system

    Publication Year: 1995, Page(s):1236 - 1247
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    We concentrate on the architectural issues of parallelizing I/O access in a disk array system by means of definition of a new, particularly flexible architecture, called partial dynamic declustering, which is fault-tolerant and offers higher levels of performance and reliability than the solutions normally used. A simulation analysis highlights the efficiency of the proposed solution in balancing ... View full abstract»

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  • On the complexity of optimal bused interconnections

    Publication Year: 1995, Page(s):1248 - 1251
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    This paper addresses the combinatorial problem of constructing a minimal cost, bused, interconnection among a set of modules (or processors). Although some work has been reported on bused interconnection between modules, the compuational complexity of the problem has not been previously addressed. We show that the optimization problem of finding a minimal cost interconnection among modules to real... View full abstract»

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  • Producing reliable initialization and test of sequential circuits with pseudorandom vectors

    Publication Year: 1995, Page(s):1251 - 1256
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper, the initialization of sequential circuits using pseudorandom input patterns is addressed. An extended Markov chain model that covers the initialization phase is proposed. This model supports the theoretical framework used to demonstrate that sequential circuits can be initialized with pseudorandom vectors. This leads to a uniform BIST approach in which initialization and testing are... View full abstract»

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  • Arithmetic unit design for neural accelerators: cost performance issues

    Publication Year: 1995, Page(s):1256 - 1260
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Arithmetic unit design is a key issue when supporting the computational requirements of neural networks. However, there is little quantitative evidence from the study of existing neural accelerators to help choose between arithmetic constructs. This paper presents an assessment of the cost-performance trade-offs between arithmetic constructs for linear neural accelerators View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org