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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct 1995

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Displaying Results 1 - 12 of 12
  • An efficient multilayer MCM router based on four-via routing

    Publication Year: 1995, Page(s):1277 - 1290
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1372 KB)

    In this paper, we present an efficient multilayer general area router, named V4R, for MCM and dense PCB designs. One unique feature of the V4R router is that it uses no more than four interconnection vias to route every net and yet produces high quality routing solutions. Another unique feature of the V4R router is it combines global routing and detailed routing in one step and produces high quali... View full abstract»

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  • A partition and resynthesis approach to testable design of large circuits

    Publication Year: 1995, Page(s):1268 - 1276
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. First, we develop a test machine embedding technique for a given gate-level implementation of a finite state machine. The test machine states are mapped onto the states of the given circuit such that a minimum number of new state variable dependencies are introduced. Th... View full abstract»

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  • Delay optimization of digital CMOS VLSI circuits by transistor reordering

    Publication Year: 1995, Page(s):1183 - 1192
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area and power dissipation. The technique can be coupled with transistor ... View full abstract»

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  • Grid adaption near moving boundaries in two dimensions for IC process simulation

    Publication Year: 1995, Page(s):1223 - 1230
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    During simulation of silicidation and oxidation, some layers are consumed (poly, silicon) and other layers grow (oxide, silicide). During these growth processes, grid must be added behind the advancing interface and removed in front of it. In a full integrated circuit process simulator, this has to be performed simultaneously with the transient solution of the diffusion equations for silicon dopan... View full abstract»

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  • The schema-based approach to workflow management

    Publication Year: 1995, Page(s):1257 - 1267
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    Workflow management encompasses a set of tools and techniques for organizing, monitoring, and automating complex processes. In this paper, we present an approach to applying workflow management techniques to design processes. Our approach is based upon a novel information model, called a task schema, that classifies the various tool and data objects used in a design process, and defines the rules ... View full abstract»

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  • VISTA-user interface, task level, and tool integration

    Publication Year: 1995, Page(s):1208 - 1222
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1664 KB)

    Succeeding an earlier paper on the data level, the Viennese Integrated System for Technology CAD Applications (VISTA), an integration and development system for Technology CAD, is presented. Starting with a short overview of TCAD methodology and existing integrated systems, portability and comprehensibility are postulated as key considerations and an application-framework architecture is proposed.... View full abstract»

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  • Active timing multilevel fault-simulation with switch-level accuracy

    Publication Year: 1995, Page(s):1241 - 1256
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT's intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagati... View full abstract»

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  • Test generation and concurrent error detection in current-mode A/D converters

    Publication Year: 1995, Page(s):1291 - 1298
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques has been employed in analog-to-digital (A/D) converters to eliminate errors caused by offset and low frequency noise and cancel the error effect. For real-time applications, however, it is rather difficult to achieve validati... View full abstract»

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  • A submicron DC MOSFET model for simulation of analog circuits

    Publication Year: 1995, Page(s):1193 - 1207
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1280 KB)

    This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of gD with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do n... View full abstract»

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  • Massively parallel electromagnetic simulation for photolithographic applications

    Publication Year: 1995, Page(s):1231 - 1240
    Cited by:  Papers (9)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    The two-dimensional massively parallel electromagnetic simulation program TEMPEST has been generalized to extend its applicability to many of the difficult problems in photolithography, metrology, and alignment. TEMPEST, which has been made available on the NCSA and other computing centers, combines together techniques for analysis of the transverse electric (TE) and the transverse magnetic (TM) p... View full abstract»

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  • Current testability analysis of feedback bridging faults in CMOS circuits

    Publication Year: 1995, Page(s):1299 - 1305
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an IDDQ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's View full abstract»

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  • On the acceleration of flow-oriented circuit clustering

    Publication Year: 1995, Page(s):1305 - 1308
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Flow-based method has been successful in producing high-quality circuit clusterings at the expense of long running time. In this paper, we explore the tradeoff between clustering quality and running time. We show that optimum flow distribution, which is a key concept of flow-based clustering, may not be indispensable if some compromise of the clustering result is allowed. By releasing the demand f... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu