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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct 1995

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Displaying Results 1 - 24 of 24
  • Three-color sensor based on amorphous n-i-p-i-n layer sequence

    Publication Year: 1995 , Page(s): 1763 - 1768
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    We present an amorphous silicon-based n-i-p-i-n three-color sensor with a layer sequence of substrate/metal/n-i-p-i-n/transparent contact. The color sensitivity (red, green and blue) is realized by applying small bias voltages within ±2 V. For the first time, this structure offers the possibility to integrate a color sensor on top of an ASIC chip, where pixel-based signal processing can be performed. Film thickness and optical band gap of the individual layers have been optimized to achieve maximum color separation. The surface of the metal-back contact is found to be critical for the performance of the sensor. A rough surface of the metal is responsible for short circuits at the common p-contact of the back-to-back p-i-n junction diodes. The steady-state I-V characteristics of the dark and photo currents have been studied. The dynamic range of the sensor is already suitable for optoelectronic applications. Sensor performance is not affected by metastable effects after prolonged light soaking. Speed limitations have been evaluated from switching experiments in the voltage mode. View full abstract»

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  • A flux-based study of carrier transport in thin-base diodes and transistors

    Publication Year: 1995 , Page(s): 1806 - 1815
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    Carrier transport in pn-junction is re-examined using McKelvey's flux method. A simple but physically based treatment of carrier transport leads to new expressions for the "law of the junction," quasi-Fermi level, I-V characteristics, base transit time, and probability of carrier backscattering from the space charge region, which are valid from the ballistic through the diffusive regimes. Comparison with Monte Carlo simulation shows that the deduced backscattering rate well describes the bias dependence. For silicon pn-junctions, the backscattering rate under reverse bias conditions is less than 5%, satisfying the Bethe condition of thermionic emission, while it rapidly increases with forward bias until drift-diffusion governs the transport. The effect of thin-base transport and backscattering on the current, carrier velocity, and distribution function is also investigated. It is found that for a base thickness less than 50 nm even silicon transistors enter the quasi-ballistic transport regime. These results should prove useful not only for fundamental understanding of the pn-junction transport, but also for careful design of advanced transistors. View full abstract»

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  • Al0.3Ga0.7As/InxGa1-xAs (0≤x≤0.25) doped-channel field-effect transistors (DCFET's)

    Publication Year: 1995 , Page(s): 1745 - 1749
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    The properties of both lattice-matched and strained doped-channel field-effect transistors (DCFET's) have been investigated in AlGaAs/InxGa1-xAs (0≤x≤0.25) heterostructures with various indium mole fractions. Through electrical characterization of grown layers in conjunction with the dc and microwave device characteristics, we observed that the introduction of a 150-Å thick strained In0.15Ga0.85As channel can enhance device performance, compared to the lattice-matched one. However, a degradation of device performance was observed for larger indium mole fractions, up to x=0.25, which is associated with strain relaxation in this highly strained channel. DCFET's also preserved a more reliable performance after biased-stress testings. View full abstract»

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  • Examination of the kink effect in InAlAs/InGaAs/InP HEMTs using sinusoidal and transient excitation

    Publication Year: 1995 , Page(s): 1717 - 1723
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The kink effect in InAlAs/InGaAs/InP HEMTs is examined in the frequency domain using sinusoidal excitation and in the time domain using voltage pulses applied to the drain of the devices. With the sinusoidal excitation below the kink voltage, two prominent output-resistance frequency-response transitions attributed to traps in the InAlAs or its interfaces were found. These transitions were examined as functions of temperature and yielded trap activation energies near 0.18 and 0.56 eV. Above the kink voltage, a single, broad transition with an activation energy near 0.24 eV was found. Using incremental voltage pulses applied to the drain, a convenient kink signature was obtained. With large voltage pulses which span the kink region, a complex nonexponential transient response was observed due to concurrent capture and emission mechanisms. HEMTs with single- and double-recessed gate structures were found to have similar output resistance dispersion characteristics. View full abstract»

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  • Dual-mode behavior of silicon heterostructure switches with third-terminal control

    Publication Year: 1995 , Page(s): 1798 - 1805
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    The performance of three-terminal silicon heterostructure switches is examined. Different types of third terminal injection are considered. The device is seen to operate in both avalanche and punch-through modes under particular circumstances. The criterion for punch-through operation is developed. View full abstract»

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  • A 40 nm gate length n-MOSFET

    Publication Year: 1995 , Page(s): 1822 - 1830
    Cited by:  Papers (36)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as Vd falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if Vd is less than or equal to 1.5 V. View full abstract»

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  • The base current degradation of poly-emitter BJTs under AC stress

    Publication Year: 1995 , Page(s): 1868 - 1871
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results. View full abstract»

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  • An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

    Publication Year: 1995 , Page(s): 1789 - 1797
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented. View full abstract»

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  • Noise performance of Si/Si1-xGex FETs

    Publication Year: 1995 , Page(s): 1841 - 1846
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs. View full abstract»

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  • High-fmax AlGaAs/InGaAs and AlGaAs/GaAs HBT's with p+/p regrown base contacts

    Publication Year: 1995 , Page(s): 1735 - 1744
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    The present paper describes a new approach to fabricating high performance HBT's with low base resistance. Their base contact resistance is reduced by using MOMBE selective growth in the extrinsic base region-a key process in the fabrication of high-fmax AlGaAs/InGaAs and AlGaAs/GaAs HBT's. A p+/p regrown base structure, which consists of a 40-nm-thick graded InGaAs strained layer and a heavily C-doped regrown contact layer, is used for the AlGaAs/InGaAs HBT's to reduce both their base transit time and base resistance, while preventing aluminum oxide incorporation at the regrowth interface. An hfe of 93, an fT of 102 GHz, and an fmax of 224 GHz are achieved for a 1.6-μm×4.6-μm HBT, together with reduced base push-out effects and improved reliability. AlGaAs/GaAs HBT's with an 80-nm-thick uniform base layer that have high fmax values ranging from 140-216 GHz are also fabricated using the selective growth technique. These results confirm the high potential of the proposed HBT's, especially for microwave and millimeter-wave applications. View full abstract»

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  • Enhanced GaAs MESFET CAD model for a wide range of temperatures

    Publication Year: 1995 , Page(s): 1724 - 1734
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    We describe a new and enhanced GaAs MESFET model suitable for implementation in computer aided design (CAD) software packages such as, for example, SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of GaAs MESFET's in a wide temperature range, from 77 K to 350°C. The current-voltage characteristics are described by a single continuous, analytical expression for all regimes of operation. The physics-based model includes effects such as velocity saturation in the channel, drain induced barrier lowering, finite output conductance in saturation, bias dependent series source and drain resistances, effects of bulk charge, bias dependent average low-field mobility, frequency dependent output conductance, backgating and sidegating, and temperature dependent model parameters. The output resistance and the transconductance are also accurately reproduced, making the model suitable for analog CAD. View full abstract»

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  • Noise suppression effect in an avalanche multiplication photodiode operating in a charge accumulation mode

    Publication Year: 1995 , Page(s): 1769 - 1774
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    A pixel configuration available to solid-state imagers using an avalanche multiplication photodiode operated in a charge accumulation mode, with each pixel as a photo-element, is proposed and stable avalanche multiplication gains over several tens are demonstrated by using a test circuit composed of discrete elements, equivalent to the pixel configuration. Moreover, it is found that the self-quenching effects inherent to the APD operating in this mode suppress the reset or avalanche induced excess noises, predominant in readout process and in charge accumulation process, respectively. These results are advantageous for a solid-state imager since the use of the avalanche multiplication simultaneously satisfies the two requirements of high sensitivity and wide dynamic range. View full abstract»

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  • An advanced model for dopant diffusion in polysilicon

    Publication Year: 1995 , Page(s): 1750 - 1755
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    A two-dimensional simulation model for dopant diffusion in polysilicon has been developed, which includes dopant clustering in grain interiors as well as in grain boundaries. The grain growth model is coupled with the diffusion coefficient of the dopants and the process temperature based on thermodynamic concepts. For high dose implantation cases the trapping/emission mechanism between grain interiors and grain boundaries and the grain growth are the major effects during thermal treatment processes. The polysilicon grains itself are assumed to be tiny squares, growing from initial size. In order to handle nonplanar semiconductor structures, we use a transformation method for the simulation area as well as for the PDEs. View full abstract»

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  • On the theory of 1/f noise of semi-insulating materials

    Publication Year: 1995 , Page(s): 1866 - 1868
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    The 1/f noise phenomena associated with devices involving semi-insulating materials, for instance GaAs MESFET's on semi-insulating GaAs, has long been a perplexing problem. In this particular case the 1/f noise corner frequency can be up to 100 MHz before the mean square noise current at the drain is dominated by the Nyquist noise associated with the channel conductance. No reasonable explanation has ever been given, although there are many different theories. 1/f noise is a common phenomena in nature and other devices involving semi-insulating materials. We propose here that this 1/f noise is a bulk phenomena associated with localized high frequency variations and long range low frequency fluctuations, the lowest frequency being limited only by the volume of the material. Specifically the proposal here is that injection of a current I into a semi-insulating material will result in a mean square noise voltage at the point of injection given by vn2~=2(kT/q)qΔfR(ωc/ω) Volts2 where ωc=1/tt, for the radian frequencies, ω, larger than ωc which is the reciprocal of the transit time of the carriers. For a long sample and long transit times then this 1/f noise voltage due to current injection will be larger than the Nyquist mean square noise of the sample alone as long as the DC voltage developed across the semi-insulating sample exceeds ((2kT/q)l2(ω/μ))12/. This theory then gives the 1/f or 1/ω frequency dependence. The dc current I might be injected for instance by the substrate current in a GaAs MESFET being injected into the semi-insulating substrate, or gate current in an IGET being injected into the gate insulator. View full abstract»

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  • A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

    Publication Year: 1995 , Page(s): 1831 - 1840
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BVCEO, optional 0.7-μm (Leff) NMOS transistors with p+ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p+ polysilicon-to-n+ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches. View full abstract»

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  • Variational aberration theory for magnetic deflection systems with curved axes at extra-large angles

    Publication Year: 1995 , Page(s): 1855 - 1862
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    Variational deflection aberration theory has been further developed for deflection systems with curved axes at extra-large deflection angles (up to 120°). The variational method allows us to calculate second- and third-order deflection aberrations with respect to a curved axis by means of gradient operations on eikonal (the function of optical length). All second- and third-order deflection aberrations have been explicitly expressed in compact and appropriate formulae suitable for computer computations. It is to be expected that the variational deflection aberration theory may be useful in designing high-quality magnetic deflection systems for high-deflection television color picture tubes. View full abstract»

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  • Electron ejection processes at insulator-semiconductor interfaces in ACTFEL display devices

    Publication Year: 1995 , Page(s): 1756 - 1762
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    Luminance, conduction current and threshold voltage of ZnS:Mn ac thin film electroluminescent display devices were measured as functions of device temperature (10 K-300 K) and risetime of the excitation voltage pulse (2 μs-50 μs). Results provided insight into the electron ejection mechanism at the insulator-phosphor interfaces. It was found that the distribution of interface state electrons at the beginning of the excitation voltage pulse varied substantially with device temperature. Pure tunneling is thought to be the dominant electron ejection mechanism at the beginning of the voltage pulse while phonon-assisted tunneling is responsible for altering the interface electron distribution during the interval between the pulses. A delay of several microseconds was observed in the build up of the transferred charge. It is attributed to the relatively small population of electrons available at the insulator-phosphor interface. View full abstract»

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  • Extraction of gate dependent source/drain resistance and effective channel length in MOS devices at 77 K

    Publication Year: 1995 , Page(s): 1863 - 1865
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A new extraction technique for obtaining the parasitic source/drain resistance and the effective channel length of an MOS device at 77 K is presented. Unlike previous methods, both parameters are assumed to vary with the gate voltage. This results in positive and physically meaningful results at any temperature. Simulation results show that, in non-LDD devices, the source/drain resistance decreases and the effective channel length increases with gate bias, indicating that the gate dependence of both parameters is inherent to MOS devices. View full abstract»

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  • A discrete element model of laser beam induced current (LBIC) due to the lateral photovoltaic effect in open-circuit HgCdTe photodiodes

    Publication Year: 1995 , Page(s): 1775 - 1782
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The non-destructive optical characterization technique of Laser-Beam-Induced-Current (LBIC) imaging has proven useful in qualitatively assessing electrically active defects and localized non-uniformities in HgCdTe materials and devices used for infrared photovoltaic arrays. To further the development of a quantitative working model for LBIC, this paper focuses on the application of the technique to photovoltaic structures that are represented by a discrete element equivalent circuit. For this particular case the LBIC signal arises due to the lateral photovoltaic effect in non-uniformly illuminated open-circuit photodiodes. The outcomes of the model predict all of the experimentally observed geometrical features of the LBIC image and signal. Furthermore, the model indicates that the LBIC signal has an extremely weak dependence on the p-n junction reverse saturation current, and shows a linear dependence with laser power. This latter feature map be useful for non-contact measurement of the quantum efficiency of individual photodiodes within a large two-dimensional focal plane array. The decay of the LBIC signal outside the physical boundary of the p-n junction is of the same form as the roll-off in the short circuit photoresponse and, therefore, can be used to extract the diffusion length of minority carriers. Experimental data is obtained from an arsenic implanted p-on-n junction fabricated on MBE grown Hg1-xCdxTe material with an x-value of 0.3. The p-on-n diode is shown to be uniform and of high quality with an R0A product of 1×108 Ω·cm2 at 77 K. The validity of the simple model developed in this paper, is confirmed by the excellent agreement with experimental results. Consequently, the LBIC technique is shown to be an appropriate diagnostic tool for non-contact quantitative analysis of semiconductor materials and devices. View full abstract»

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  • ESD reliability and protection schemes in SOI CMOS output buffers

    Publication Year: 1995 , Page(s): 1816 - 1821
    Cited by:  Papers (5)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate. View full abstract»

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  • A 1/4-inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

    Publication Year: 1995 , Page(s): 1783 - 1788
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 μm (H)×5.6 μm (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV). View full abstract»

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  • DRAM plate electrode bias optimization for reducing leakage current in UV-O3 and O2 annealed CVD deposited Ta2O5 dielectric films

    Publication Year: 1995 , Page(s): 1871 - 1872
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O3 and O2 annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of Vcc/2. Ta2O5 films with 3.9 nm effective gate oxide, 8.5 fF/μm2 capacitance and <0.3 μA/cm2 leakage at 100°C and 3.3 V supply are demonstrated. View full abstract»

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  • A behavioral circuit simulation model for high-power GaAs Schottky diodes

    Publication Year: 1995 , Page(s): 1847 - 1854
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    This paper proposes a physically based behavioral circuit simulation model for high-power GaAs Schottky diodes which is valid over all regions of operation. No conditional statements are needed to define the regions of operation. A new and more accurate method of obtaining depletion capacitance model parameters from the measured capacitance values is proposed. A simple current- and temperature-dependent resistance model is used to model the nonlinear diode resistance as well as contact and packaging resistances. The validity of the model is demonstrated under various DC and transient switching conditions. Simulation results are compared with the experimental data obtained from a 200 V GaAs Schottky diode. The diode model is tested at various temperatures in different test circuits and the simulation results are shown to be in excellent agreement with the measured data under static and dynamic switching conditions. The model can be easily implemented in other circuit simulators. View full abstract»

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  • The influence of an LIGBT on CMOS latch up in power integrated circuit

    Publication Year: 1995 , Page(s): 1873 - 1874
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    The latch up characteristics of a CMOS adjacent to a high voltage lateral insulated gate bipolar transistor (LIGBT) have been experimentally investigated. While it has been found that the holding voltage and holding current of the CMOS do not strongly depend on the power device operation, the triggering voltage has been found to be critical to the power device operation. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego